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| DATA SHEET MOS INTEGRATED CIRCUIT PD161622 396 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM DESCRIPTION The PD161622 is a TFT-LCD source driver that includes display RAM. This driver has 396 outputs, a display RAM capacity of 371,712 bits (132 pixels x 16 bits x 176 lines) and, can provide a 65,536-color display. FEATURES * TFT-LCD driver with on-chip display RAM * Logic power supply voltage: 2.5 to 3.6 V * Driver power supply voltage: 4.3 to 5.5 V * Display RAM: 132 x 16 x 176 bits * Driver outputs: 396 output * CPU interface: Serial, 8-bit/16-bit parallel interface selectable * Colors: 65,536 colors/pixel * On-chip VCOM generator * On-chip timing generator * On-chip oscillator ORDERING INFORMATION Part Number Package Chip PD161622P Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15649EJ2V0DS00 (2nd edition) Date Published August 2003 NS CP(K) Printed in Japan The mark shows major revised points. 2001 PD161622 1. BLOCK DIAGRAM V0 to V5 VRH VCC1 VCC2 VSS VS S1 S2 S3 S4 S395 S396 VRL1 VRL2 LCD drive circuit Gray scale generator CVPH CVPL CVNH CVNL Decoder Level shifter (2.5 V Display data latch 5 V) LCD timing control Display data RAM (132 x 16 x 176 bits) Calibrator Oscillator Arbiter BGR OSCIN OSCOUT RSEL BGRIN Internal timing generator Command decoder D/A converter Address decoder / controller Data register VCOM generator DAC0 to DAC7 VCOMR FBRSEL I/O buffer Gate control PS control Remark /xxx indicates active low signal. 2 PSX /CS /RESET /RD(E) /WR(R, /W) C86 D8 to D15 D7 (SI) D6 (SCL) D0 to D5 RS IP0 to IP3 OP0 to OP7 CSTB TOUT0 to TOUT15 TSTx TOSCx TBSELx TBGR Data Sheet S15649EJ2V0DS VCOM VCOUT1 VCOUT2 LPMP DCON VCD11 VCD12 VCD2 VCE RGONP LPMG GOE1 GOE2 GSTB GCLK RGONG PD161622 2. PIN CONFIGURATION (Pad Layout) Chip size: 3.60 x 17.80 mm2 TYP. Bump size (output type A): 35 x 94 m2 TYP. 2 Bump size (input & dummy): 80 x 86 m TYP. Alignment mark (mark center, unit: m) X M1 M2 M3 -1615 -1615 1435 Y 8715 -8715 -8715 562 559 558 Alignment mark reference (unit: m) 1 72 72 60 204 72 72 204 60 Y(+ X(+ 130 m 141 142 145 146 Data Sheet S15649EJ2V0DS 41.5 m 41.5 m 3 PD161622 Table 2-1. Pad Layout (1/4) P N. in o 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 P Nm P dT e in a e a yp DMY UM B DMY UM B DMY UM B T U1 OT5 B T U1 OT4 B T U1 OT3 B T U1 OT2 B T U1 OT1 B T U1 OT0 B T U9 OT B T U8 OT B T U7 OT B T U6 OT B T U5 OT B T U4 OT B T U3 OT B T U2 OT B T U1 OT B T U0 OT B V S OE S (M D) B T T IH SV L B TTTT S RS B T S SL O C EO B T S SL O C EI B T SI OC B T SO OC B V C(M D C1 OE B RE SL B V S OE S (M D) B OC U S OT B V S OE S (M D) B OC S IN B V S OE S (M D) B CT SB B D5 1 B D4 1 B D3 1 B D2 1 B D1 1 B D0 1 B D 9 B D 8 B D (S 7 I) B D (S L 6 C) B D 5 B D 4 B D 3 B D 2 B D 1 B D 0 B V S OE S (M D) B /C S B /RS T EE B R S B /W (R ) R ,/W B /R (E D) B VC C2 B PX S B C6 8 B V S OE S (M D) B X[ ] m -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 Y[ ] m 8 9 .0 30 0 8 7 .0 20 0 8 5 .0 10 0 8 3 .0 00 0 7 1 .0 90 0 7 9 .0 70 0 7 7 .0 60 0 7 5 .0 50 0 7 3 .0 40 0 7 1 .0 30 0 7 9 .0 10 0 7 7 .0 00 0 6 5 .0 90 0 6 3 .0 80 0 6 1 .0 70 0 6 9 .0 50 0 6 7 .0 40 0 6 5 .0 30 0 6 3 .0 20 0 6 1 .0 10 0 5 9 .0 90 0 5 7 .0 80 0 5 5 .0 70 0 5 3 .0 60 0 5 1 .0 50 0 5 9 .0 30 0 5 7 .0 20 0 5 5 .0 10 0 5 3 .0 00 0 4 1 .0 90 0 4 9 .0 70 0 4 7 .0 60 0 4 5 .0 50 0 4 3 .0 40 0 4 1 .0 30 0 4 9 .0 10 0 4 7 .0 00 0 3 5 .0 90 0 3 3 .0 80 0 3 1 .0 70 0 3 9 .0 50 0 3 7 .0 40 0 3 5 .0 30 0 3 3 .0 20 0 3 1 .0 10 0 2 9 .0 90 0 2 7 .0 80 0 2 5 .0 70 0 2 3 .0 60 0 2 1 .0 50 0 2 9 .0 30 0 2 7 .0 20 0 2 5 .0 10 0 2 3 .0 00 0 1 1 .0 90 0 1 9 .0 70 0 1 7 .0 60 0 1 5 .0 50 0 1 3 .0 40 0 1 1 .0 30 0 P N. in o 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 10 2 P Nm P dT e in a e a yp VE C B VD C2 B V D2 C1 B V D1 C1 B LM PP B R OP GN B DO CN B V OT C U2 B VS S B VC C2 B VC C1 B VS S B VS S B CN VL B CN VH B CP VL B CP VH B V S B V S B VS S B V OT C U1 B V OT C U1 B VC C1 B VC C1 B VO CM B DMY UM B DMY UM B V S OE S (M D) B V OR CM B BR G IN B V C(M D C1 OE B F RE B SL B V S OE S (M D) B VH R B V 0 B V 1 B V 2 B V 3 B V 4 B V 5 B VL R1 B VL R2 B V S OE S (M D) B T SL B E1 B T SL B E2 B TG BR B DC A7 B DC A6 B DC A5 B DC A4 B DC A3 B DC A2 B DC A1 B DC A0 B V S OE S (M D) B O0 P B O1 P B O2 P B O3 P B O4 P B X[ ] m -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 Y[ ] m 1 9 .0 10 0 1 7 .0 00 0 90 0 5 .0 80 0 3 .0 70 0 1 .0 50 0 9 .0 40 0 7 .0 30 0 5 .0 20 0 3 .0 10 0 1 .0 -1 .0 00 -1 0 0 3 .0 -2 0 0 5 .0 -3 0 0 7 .0 -4 0 0 9 .0 -6 0 0 1 .0 -7 0 0 3 .0 -8 0 0 5 .0 -9 0 0 7 .0 -1 9 .0 00 0 -1 1 .0 20 0 -1 3 .0 30 0 -1 5 .0 40 0 -1 7 .0 50 0 -1 9 .0 60 0 -1 1 .0 80 0 -1 3 .0 90 0 -2 5 .0 00 0 -2 7 .0 10 0 -2 9 .0 20 0 -2 1 .0 40 0 -2 3 .0 50 0 -2 5 .0 60 0 -2 7 .0 70 0 -2 9 .0 80 0 -3 1 .0 00 0 -3 3 .0 10 0 -3 5 .0 20 0 -3 7 .0 30 0 -3 9 .0 40 0 -3 1 .0 60 0 -3 3 .0 70 0 -3 5 .0 80 0 -3 7 .0 90 0 -4 9 .0 00 0 -4 1 .0 20 0 -4 3 .0 30 0 -4 5 .0 40 0 -4 7 .0 50 0 -4 9 .0 60 0 -4 1 .0 80 0 -4 3 .0 90 0 -5 5 .0 00 0 -5 7 .0 10 0 -5 9 .0 20 0 -5 1 .0 40 0 -5 3 .0 50 0 -5 5 .0 60 0 -5 7 .0 70 0 -5 9 .0 80 0 P N. in o 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 10 6 11 6 12 6 13 6 14 6 15 6 16 6 17 6 18 6 19 6 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 7 19 7 10 8 P Nm PdT e in a e a yp O5 P B O6 P B O7 P B V C(M D C1 OE B IP 0 B V S OE S (M D) B IP 1 B V C(M D C1 OE B IP 2 B V S OE S (M D) B IP 3 B V C(M D C1 OE B GT SB B GL CK B GE O1 B GE O2 B R OG GN B LM PG B DMY UM B DMY UM B DMY UM B DMY UM B DMY UM B DMY UM B DMY UM B DMY UM B DMY UM A DMY UM A S9 36 A S9 35 A S9 34 A S9 33 A S9 32 A S9 31 A S9 30 A S8 39 A S8 38 A S8 37 A S8 36 A S8 35 A S8 34 A S8 33 A S8 32 A S8 31 A S8 30 A S7 39 A S7 38 A S7 37 A S7 36 A S7 35 A S7 34 A S7 33 A S7 32 A S7 31 A S7 30 A S6 39 A S6 38 A S6 37 A S6 36 A S6 35 A X[ ] m -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 7 .0 64 0 -1 5 .0 30 0 -5 0 0 1 .0 30 0 3 .0 1 7 .0 10 0 1 7 .0 60 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m -6 1 .0 00 0 -6 3 .0 10 0 -6 5 .0 20 0 -6 7 .0 30 0 -6 9 .0 40 0 -6 1 .0 60 0 -6 3 .0 70 0 -6 5 .0 80 0 -6 7 .0 90 0 -7 9 .0 00 0 -7 1 .0 20 0 -7 3 .0 30 0 -7 5 .0 40 0 -7 7 .0 50 0 -7 9 .0 60 0 -7 1 .0 80 0 -7 3 .0 90 0 -8 5 .0 00 0 -8 7 .0 10 0 -8 9 .0 20 0 -8 1 .0 40 0 -8 7 .0 74 0 -8 7 .0 74 0 -8 7 .0 74 0 -8 7 .0 74 0 -8 0 .0 60 0 -8 2 .0 50 0 -8 7 .5 48 0 -8 3 .0 47 0 -8 9 .5 35 0 -8 5 .0 34 0 -8 1 .5 32 0 -8 7 .0 21 0 -8 2 .5 29 0 -8 8 .0 18 0 -8 4 .5 16 0 -8 0 .0 15 0 -8 6 .5 03 0 -8 2 .0 02 0 -7 8 .5 90 0 -7 3 .0 99 0 -7 9 .5 87 0 -7 5 .0 86 0 -7 1 .5 84 0 -7 7 .0 73 0 -7 3 .5 71 0 -7 9 .0 60 0 -7 4 .5 68 0 -7 0 .0 67 0 -7 6 .5 55 0 -7 2 .0 54 0 -7 8 .5 42 0 -7 4 .0 41 0 -7 9 .5 39 0 -7 5 .0 38 0 -7 1 .5 36 0 -7 7 .0 25 0 -7 3 .5 23 0 -7 9 .0 12 0 -7 5 .5 10 0 4 Data Sheet S15649EJ2V0DS PD161622 Table 2-1. Pad Layout (2/4) P N. in o 11 8 12 8 13 8 14 8 15 8 16 8 17 8 18 8 19 8 10 9 11 9 12 9 13 9 14 9 15 9 16 9 17 9 18 9 19 9 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 0 20 1 21 1 22 1 23 1 24 1 25 1 26 1 27 1 28 1 29 1 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 3 29 3 20 4 P Nm in a e S6 34 S6 33 S6 32 S6 31 S6 30 S5 39 S5 38 S5 37 S5 36 S5 35 S5 34 S5 33 S5 32 S5 31 S5 30 S4 39 S4 38 S4 37 S4 36 S4 35 S4 34 S4 33 S4 32 S4 31 S4 30 S3 39 S3 38 S3 37 S3 36 S3 35 S3 34 S3 33 S3 32 S3 31 S3 30 S2 39 S2 38 S2 37 S2 36 S2 35 S2 34 S2 33 S2 32 S2 31 S2 30 S1 39 S1 38 S1 37 S1 36 S1 35 S1 34 S1 33 S1 32 S1 31 S1 30 S0 39 S0 38 S0 37 S0 36 S0 35 P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A m X[ ] 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m -7 0 .0 19 0 -7 6 .5 07 0 -7 2 .0 06 0 -6 8 .5 94 0 -6 4 .0 93 0 -6 0 .5 91 0 -6 6 .0 80 0 -6 1 .5 88 0 -6 7 .0 77 0 -6 3 .5 75 0 -6 9 .0 64 0 -6 5 .5 62 0 -6 1 .0 61 0 -6 6 .5 59 0 -6 2 .0 58 0 -6 8 .5 46 0 -6 4 .0 45 0 -6 0 .5 43 0 -6 6 .0 32 0 -6 2 .5 30 0 -6 7 .0 29 0 -6 3 .5 27 0 -6 9 .0 16 0 -6 5 .5 14 0 -6 1 .0 13 0 -6 7 .5 01 0 -6 3 .0 00 0 -5 8 .5 98 0 -5 4 .0 97 0 -5 0 .5 95 0 -5 6 .0 84 0 -5 2 .5 82 0 -5 8 .0 71 0 -5 3 .5 79 0 -5 9 .0 68 0 -5 5 .5 66 0 -5 1 .0 65 0 -5 7 .5 53 0 -5 3 .0 52 0 -5 9 .5 40 0 -5 4 .0 49 0 -5 0 .5 47 0 -5 6 .0 36 0 -5 2 .5 34 0 -5 8 .0 23 0 -5 4 .5 21 0 -5 0 .0 20 0 -5 5 .5 18 0 -5 1 .0 17 0 -5 7 .5 05 0 -5 3 .0 04 0 -4 9 .5 92 0 -4 5 .0 91 0 -4 0 .5 99 0 -4 6 .0 88 0 -4 2 .5 86 0 -4 8 .0 75 0 -4 4 .5 73 0 -4 0 .0 72 0 -4 6 .5 60 0 P N. in o 21 4 22 4 23 4 24 4 25 4 26 4 27 4 28 4 29 4 20 5 21 5 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 20 6 21 6 22 6 23 6 24 6 25 6 26 6 27 6 28 6 29 6 20 7 21 7 22 7 23 7 24 7 25 7 26 7 27 7 28 7 29 7 20 8 21 8 22 8 23 8 24 8 25 8 26 8 27 8 28 8 29 8 20 9 21 9 22 9 23 9 24 9 25 9 26 9 27 9 28 9 29 9 30 0 P Nm in a e S0 34 S0 33 S0 32 S0 31 S0 30 S9 29 S9 28 S9 27 S9 26 S9 25 S9 24 S9 23 S9 22 S9 21 S9 20 S8 29 S8 28 S8 27 S8 26 S8 25 S8 24 S8 23 S8 22 S8 21 S8 20 S7 29 S7 28 S7 27 S7 26 S7 25 S7 24 S7 23 S7 22 S7 21 S7 20 S6 29 S6 28 S6 27 S6 26 S6 25 S6 24 S6 23 S6 22 S6 21 S6 20 S5 29 S5 28 S5 27 S5 26 S5 25 S5 24 S5 23 S5 22 S5 21 S5 20 S4 29 S4 28 S4 27 S4 26 S4 25 P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A X[ ] m 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m -4 1 .0 69 0 -4 7 .5 57 0 -4 3 .0 56 0 -4 9 .5 44 0 -4 5 .0 43 0 -4 1 .5 41 0 -4 7 .0 30 0 -4 2 .5 38 0 -4 8 .0 27 0 -4 4 .5 25 0 -4 0 .0 24 0 -4 6 .5 12 0 -4 2 .0 11 0 -4 7 .5 09 0 -4 3 .0 08 0 -3 9 .5 96 0 -3 5 .0 95 0 -3 1 .5 93 0 -3 7 .0 82 0 -3 3 .5 80 0 -3 8 .0 79 0 -3 4 .5 77 0 -3 0 .0 76 0 -3 6 .5 64 0 -3 2 .0 63 0 -3 8 .5 51 0 -3 4 .0 50 0 -3 9 .5 48 0 -3 5 .0 47 0 -3 1 .5 45 0 -3 7 .0 34 0 -3 3 .5 32 0 -3 9 .0 21 0 -3 4 .5 29 0 -3 0 .0 28 0 -3 6 .5 16 0 -3 2 .0 15 0 -3 8 .5 03 0 -3 4 .0 02 0 -3 0 .5 00 0 -2 5 .0 99 0 -2 1 .5 97 0 -2 7 .0 86 0 -2 3 .5 84 0 -2 9 .0 73 0 -2 5 .5 71 0 -2 1 .0 70 0 -2 6 .5 68 0 -2 2 .0 67 0 -2 8 .5 55 0 -2 4 .0 54 0 -2 0 .5 52 0 -2 6 .0 41 0 -2 1 .5 49 0 -2 7 .0 38 0 -2 3 .5 36 0 -2 9 .0 25 0 -2 5 .5 23 0 -2 1 .0 22 0 -2 7 .5 10 0 P N. in o 31 0 32 0 33 0 34 0 35 0 36 0 37 0 38 0 39 0 30 1 31 1 32 1 33 1 34 1 35 1 36 1 37 1 38 1 39 1 30 2 31 2 32 2 33 2 34 2 35 2 36 2 37 2 38 2 39 2 30 3 31 3 32 3 33 3 34 3 35 3 36 3 37 3 38 3 39 3 30 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 30 5 31 5 32 5 33 5 34 5 35 5 36 5 37 5 38 5 39 5 30 6 P Nm in a e S4 24 S4 23 S4 22 S4 21 S4 20 S3 29 S3 28 S3 27 S3 26 S3 25 S3 24 S3 23 S3 22 S3 21 S3 20 S2 29 S2 28 S2 27 S2 26 S2 25 S2 24 S2 23 S2 22 S2 21 S2 20 S1 29 S1 28 S1 27 S1 26 S1 25 S1 24 S1 23 S1 22 S1 21 S1 20 S0 29 S0 28 S0 27 S0 26 S0 25 S0 24 S0 23 S0 22 S0 21 S0 20 S9 19 S9 18 S9 17 S9 16 S9 15 S9 14 S9 13 DMY UM DMY UM DMY UM DMY UM DMY UM DMY UM DMY UM DMY UM P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A X[ ] m 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m -2 2 .0 19 0 -2 8 .5 07 0 -2 4 .0 06 0 -2 0 .5 04 0 -1 6 .0 93 0 -1 2 .5 91 0 -1 8 .0 80 0 -1 3 .5 88 0 -1 9 .0 77 0 -1 5 .5 75 0 -1 1 .0 74 0 -1 7 .5 62 0 -1 3 .0 61 0 -1 8 .5 59 0 -1 4 .0 58 0 -1 0 .5 56 0 -1 6 .0 45 0 -1 2 .5 43 0 -1 8 .0 32 0 -1 4 .5 30 0 -1 9 .0 29 0 -1 5 .5 27 0 -1 1 .0 26 0 -1 7 .5 14 0 -1 3 .0 13 0 -1 9 .5 01 0 -1 5 .0 00 0 -1 0 .5 08 0 -9 7 0 6 .0 -9 5 0 2 .5 -8 4 0 8 .0 -8 2 0 4 .5 -8 1 0 0 .0 -7 9 0 5 .5 -7 8 0 1 .0 -6 6 0 7 .5 -6 5 0 3 .0 -5 3 0 9 .5 -5 2 0 5 .0 -5 0 0 1 .5 -4 9 0 6 .0 -4 7 0 2 .5 -3 6 0 8 .0 -3 4 0 4 .5 -3 3 0 0 .0 -2 1 0 6 .5 -2 0 0 2 .0 -1 8 0 7 .5 -1 7 0 3 .0 -9 .5 50 -5 .0 40 -1 .5 20 2 .0 90 7 .5 00 12 0 1 .0 13 0 5 .5 15 0 9 .0 26 0 3 .5 28 0 7 .0 39 0 1 .5 Data Sheet S15649EJ2V0DS 5 PD161622 Table 2-1. Pad Layout (3/4) P N. in o 31 6 32 6 33 6 34 6 35 6 36 6 37 6 38 6 39 6 30 7 31 7 32 7 33 7 34 7 35 7 36 7 37 7 38 7 39 7 30 8 31 8 32 8 33 8 34 8 35 8 36 8 37 8 38 8 39 8 30 9 31 9 32 9 33 9 34 9 35 9 36 9 37 9 38 9 39 9 40 0 41 0 42 0 43 0 44 0 45 0 46 0 47 0 48 0 49 0 40 1 41 1 42 1 43 1 44 1 45 1 46 1 47 1 48 1 49 1 40 2 P Nm in a e DMY UM DMY UM DMY UM DMY UM S9 12 S9 11 S9 10 S8 19 S8 18 S8 17 S8 16 S8 15 S8 14 S8 13 S8 12 S8 11 S8 10 S7 19 S7 18 S7 17 S7 16 S7 15 S7 14 S7 13 S7 12 S7 11 S7 10 S6 19 S6 18 S6 17 S6 16 S6 15 S6 14 S6 13 S6 12 S6 11 S6 10 S5 19 S5 18 S5 17 S5 16 S5 15 S5 14 S5 13 S5 12 S5 11 S5 10 S4 19 S4 18 S4 17 S4 16 S4 15 S4 14 S4 13 S4 12 S4 11 S4 10 S3 19 S3 18 S3 17 P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A m X[ ] 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m 31 0 6 .0 42 0 0 .5 44 0 4 .0 45 0 8 .5 57 0 2 .0 58 0 6 .5 60 0 1 .0 61 0 5 .5 63 0 9 .0 74 0 3 .5 76 0 7 .0 87 0 1 .5 89 0 5 .0 90 0 0 .5 92 0 4 .0 93 0 8 .5 1 2 .0 05 0 1 6 .5 06 0 1 0 .0 18 0 1 4 .5 19 0 1 9 .0 11 0 1 3 .5 22 0 1 7 .0 24 0 1 1 .5 35 0 1 5 .0 37 0 1 9 .5 38 0 1 4 .0 40 0 1 8 .5 41 0 1 2 .0 53 0 1 6 .5 54 0 1 0 .0 66 0 1 4 .5 67 0 1 8 .0 69 0 1 3 .5 70 0 1 7 .0 72 0 1 1 .5 83 0 1 5 .0 85 0 1 9 .5 86 0 1 3 .0 98 0 1 7 .5 99 0 2 2 .0 01 0 2 6 .5 02 0 2 0 .0 14 0 2 4 .5 15 0 2 8 .0 17 0 2 2 .5 28 0 2 7 .0 20 0 2 1 .5 31 0 2 5 .0 33 0 2 9 .5 34 0 2 3 .0 46 0 2 7 .5 47 0 2 1 .0 59 0 2 6 .5 50 0 2 0 .0 62 0 2 4 .5 63 0 2 8 .0 65 0 2 2 .5 76 0 2 6 .0 78 0 2 0 .5 89 0 P N. in o 41 2 42 2 43 2 44 2 45 2 46 2 47 2 48 2 49 2 40 3 41 3 42 3 43 3 44 3 45 3 46 3 47 3 48 3 49 3 40 4 41 4 42 4 43 4 44 4 45 4 46 4 47 4 48 4 49 4 40 5 41 5 42 5 43 5 44 5 45 5 46 5 47 5 48 5 49 5 40 6 41 6 42 6 43 6 44 6 45 6 46 6 47 6 48 6 49 6 40 7 41 7 42 7 43 7 44 7 45 7 46 7 47 7 48 7 49 7 40 8 P Nm in a e S3 16 S3 15 S3 14 S3 13 S3 12 S3 11 S3 10 S2 19 S2 18 S2 17 S2 16 S2 15 S2 14 S2 13 S2 12 S2 11 S2 10 S1 19 S1 18 S1 17 S1 16 S1 15 S1 14 S1 13 S1 12 S1 11 S1 10 S0 19 S0 18 S0 17 S0 16 S0 15 S0 14 S0 13 S0 12 S0 11 S0 10 S9 9 S8 9 S7 9 S6 9 S5 9 S4 9 S3 9 S2 9 S1 9 S0 9 S9 8 S8 8 S7 8 S6 8 S5 8 S4 8 S3 8 S2 8 S1 8 S0 8 S9 7 S8 7 S7 7 P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A X[ ] m 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m 2 5 .0 81 0 2 9 .5 82 0 2 3 .0 94 0 2 7 .5 95 0 3 1 .0 07 0 3 5 .5 08 0 3 0 .0 10 0 3 4 .5 11 0 3 8 .0 13 0 3 2 .5 24 0 3 6 .0 26 0 3 0 .5 37 0 3 4 .0 39 0 3 9 .5 30 0 3 3 .0 42 0 3 7 .5 43 0 3 1 .0 55 0 3 5 .5 56 0 3 9 .0 58 0 3 3 .5 69 0 3 8 .0 61 0 3 2 .5 72 0 3 6 .0 74 0 3 0 .5 85 0 3 4 .0 87 0 3 8 .5 88 0 3 3 .0 90 0 3 7 .5 91 0 4 1 .0 03 0 4 5 .5 04 0 4 9 .0 06 0 4 3 .5 17 0 4 7 .0 19 0 4 2 .5 20 0 4 6 .0 22 0 4 0 .5 33 0 4 4 .0 35 0 4 8 .5 36 0 4 2 .0 48 0 4 6 .5 49 0 4 1 .0 51 0 4 5 .5 52 0 4 9 .0 54 0 4 3 .5 65 0 4 7 .0 67 0 4 1 .5 78 0 4 6 .0 70 0 4 0 .5 81 0 4 4 .0 83 0 4 8 .5 84 0 4 2 .0 96 0 4 6 .5 97 0 5 0 .0 09 0 5 5 .5 00 0 5 9 .0 02 0 5 3 .5 13 0 5 7 .0 15 0 5 1 .5 26 0 5 5 .0 28 0 5 9 .5 29 0 P N. in o 41 8 42 8 43 8 44 8 45 8 46 8 47 8 48 8 49 8 40 9 41 9 42 9 43 9 44 9 45 9 46 9 47 9 48 9 49 9 50 0 51 0 52 0 53 0 54 0 55 0 56 0 57 0 58 0 59 0 50 1 51 1 52 1 53 1 54 1 55 1 56 1 57 1 58 1 59 1 50 2 51 2 52 2 53 2 54 2 55 2 56 2 57 2 58 2 59 2 50 3 51 3 52 3 53 3 54 3 55 3 56 3 57 3 58 3 59 3 50 4 P Nm in a e S6 7 S5 7 S4 7 S3 7 S2 7 S1 7 S0 7 S9 6 S8 6 S7 6 S6 6 S5 6 S4 6 S3 6 S2 6 S1 6 S0 6 S9 5 S8 5 S7 5 S6 5 S5 5 S4 5 S3 5 S2 5 S1 5 S0 5 S9 4 S8 4 S7 4 S6 4 S5 4 S4 4 S3 4 S2 4 S1 4 S0 4 S9 3 S8 3 S7 3 S6 3 S5 3 S4 3 S3 3 S2 3 S1 3 S0 3 S9 2 S8 2 S7 2 S6 2 S5 2 S4 2 S3 2 S2 2 S1 2 S0 2 S9 1 S8 1 S7 1 P dT e a yp A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A X[ ] m 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 Y[ ] m 5 4 .0 31 0 5 8 .5 32 0 5 2 .0 44 0 5 6 .5 45 0 5 0 .0 57 0 5 4 .5 58 0 5 9 .0 50 0 5 3 .5 61 0 5 7 .0 63 0 5 1 .5 74 0 5 5 .0 76 0 5 9 .5 77 0 5 3 .0 89 0 5 8 .5 80 0 5 2 .0 92 0 5 6 .5 93 0 6 0 .0 05 0 6 4 .5 06 0 6 8 .0 08 0 6 2 .5 19 0 6 7 .0 11 0 6 1 .5 22 0 6 5 .0 24 0 6 9 .5 25 0 6 3 .0 37 0 6 7 .5 38 0 6 2 .0 40 0 6 6 .5 41 0 6 0 .0 53 0 6 4 .5 54 0 6 8 .0 56 0 6 2 .5 67 0 6 6 .0 69 0 6 1 .5 70 0 6 5 .0 72 0 6 9 .5 73 0 6 3 .0 85 0 6 7 .5 86 0 6 1 .0 98 0 6 5 .5 99 0 7 0 .0 01 0 7 4 .5 02 0 7 8 .0 04 0 7 2 .5 15 0 7 6 .0 17 0 7 0 .5 28 0 7 5 .0 20 0 7 9 .5 21 0 7 3 .0 33 0 7 7 .5 34 0 7 1 .0 46 0 7 5 .5 47 0 7 9 .0 49 0 7 4 .5 50 0 7 8 .0 52 0 7 2 .5 63 0 7 6 .0 65 0 7 0 .5 76 0 7 4 .0 78 0 7 8 .5 79 0 6 Data Sheet S15649EJ2V0DS PD161622 Table 2-1. Pad Layout (4/4) P N. in o 51 4 52 4 53 4 54 4 55 4 56 4 57 4 58 4 59 4 50 5 51 5 52 5 53 5 54 5 55 5 56 5 57 5 58 5 59 5 50 6 51 6 52 6 P Nm in a e S6 1 S5 1 S4 1 S3 1 S2 1 S1 1 S0 1 S 9 S 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 DMY UM DMY UM DMY UM DMY UM DMY UM DMY UM P dT e a yp A A A A A A A A A A A A A A A A A B B B B B m X[ ] 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 4 .0 50 0 1 7 .0 60 0 1 7 .0 60 0 1 2 .0 20 0 30 0 8 .0 -4 0 0 6 .0 -1 0 .0 30 0 Y[ ] m 7 3 .0 81 0 7 7 .5 82 0 7 1 .0 94 0 7 5 .5 95 0 7 9 .0 97 0 8 3 .5 08 0 8 8 .0 00 0 8 2 .5 11 0 8 6 .0 13 0 8 0 .5 24 0 8 4 .0 26 0 8 8 .5 27 0 8 2 .0 39 0 8 7 .5 30 0 8 1 .0 42 0 8 5 .5 43 0 8 9 .0 45 0 8 7 .0 55 0 8 7 .0 74 0 8 7 .0 74 0 8 7 .0 74 0 8 7 .0 74 0 Data Sheet S15649EJ2V0DS 7 PD161622 3. PIN FUNCTIONS 3.1 Power Supply System Pins Symbol VCC1 VCC2 VS VSS V0 to V5 VRH VRL1, VRL2 Pin Name Logic power supply I/O power supply Driver power supply Ground Power supply for -curve correction Pad No. 71, 83, 84 57, 70 78, 79 69, 72, 72, 80 95 to 100, 94, 101, 102 I/O - - - - - Power supply pin for logic circuit Power supply pin for I/O buffer Power supply pin for driver circuit Ground pin for logic and driver circuits The PD161622 includes power supplies and resistors for the -curve, so if the characteristics of the -curve and LCD panel in the PD161622 match, leave V0 to V5, VRH, VRL1, VRL2 open. If some kind of correction is required, adjust the -curve by connecting resistors between the V0 to V5, VRH, VRL1, VRL2 pins (see 5.9 -Curve Correction Power Supply Circuit for Cases of Unbalanced Driving). VCC1(MODE) Mode setting pull-up power-supply VSS(MODE) Mode setting pull-down power-supply 27, 91, 124, 128, 132 20, 29, 31, 33, 51, 60, 88, 93, 103, 115, 126, 130 Function - - Pull-up power-supply pin for mode setting Pull-down power-supply pin for mode setting 3.2 Logic System Pins Symbol PSX Pin Name CPU interface selection Pad No. 58 I/O Function Input These pins are used to select the CPU interface mode. PSX = H: Parallel interface PSX = L: Serial interface (1/2) When the parallel interface is selected, this data but width can be changed /CS Chip select 52 between 8 bits and 16 bits by using BMD of index register 5 (R5). Input This pin is used for chip select signals. When /CS = L, the chip is active and can perform data input/output operations including command and data I/O. /RESET Reset 53 Input When /RESET is low, an internal reset is performed. The reset operation is executed at the /RESET signal level. Be sure to perform reset via this pin at power application. /RD (E) Read (enable) 56 Input When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is low. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable read/write operations. /WR (R, /W) Write (read/write) 55 Input When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. Data is written at the rising edge of this signal. When M68 series parallel data transfer (R, /W) and serial data has been selected, this pin is used to determine the direction of data transfer. L: Write H: Read C86 Select interface 59 Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). L: Selects i80 series CPU mode H: Selects M68 series CPU mode 8 Data Sheet S15649EJ2V0DS PD161622 (2/2) Symbol D0 to D5, D8 to D15, D6 (SCL), D7 (SI) RS (serial clock) (serial data input) Index register/, data/command selection 54 Input Pin Name Data bus Pad No. 50 to 35 I/O I/O Function These pins comprise 16-bit bi-directional data. When the serial interface has been selected (PSX = L), D7 functions as a serial data input pin (SI), D6 functions as a serial clock input pin (SCL). In either case, pins D0 to D7 and D8 to D15 are in high impedance mode. When the chip is not selected, D0 to D15 are in high impedance mode. When parallel data transfer has been selected, this pin is usually connected to the least significant bit of the standard CPU address bus and is used to distinguish between data from index registers and data/commands. RS = H: Indicates that data from D0 to D15 is data/command RS = L: Indicates that data from D0 to D7 is index register contents Also, when serial data transfer is selected, the level of the RS pin is fetched at the rising edge of the eighth clock of the serial clock and whether the data is index register contents or data/command is distinguished. RS = H: Indicates that the data input to SI is data/command. RS = L: Indicates that the data input to SI is index register contents. IP0 to IP3 Input port 125, 127, 129, 131 OP0 to OP7 RSEL Oscillation signal select 28 Input Output port 116 to 123 Output Input This is a general-purpose input port. The status of these pins (H or L) can be read via a command. Because this is a CMOS input, do not leave open. This is a general-purpose output port. The status of these pins (H or L) can be write via a command. Leave open when in unused. This pin is for oscillation signal selection. When in used external resistance connection oscillator circuit, this pin set H. When in used internal oscillator circuit, this pin set L. RSEL = H: External resistance connection oscillator circuit select RSEL = L: CR internal oscillator circuit select OSCIN Oscillation signal 32 Input This pin is for oscillation signal input. RSEL = H: Connect 51 k resistance between OSCIN and OSCOUT. RSEL = L: Leave open OSCOUT Oscillation signal 30 Output This pin is for oscillation signal input. RSEL = H: Connect 51 k resistance between OSCIN and OSCOUT. RSEL = L: Leave open CSTB GSTB logic signal 34 Output This pin outputs STB signal for gate driver leveled by interface power supply voltage (VCC2). This output signal is reverse signal of GSTB. Data Sheet S15649EJ2V0DS 9 PD161622 3.3 Gate Driver IC Control Pins Symbol LPMG GOE1 Pin Name Low power mode signal OE1 output for gate driver GOE2 OE2 output for gate driver GSTB STB output for gate driver 133 136 Pad No. 138 135 I/O Function Output This is an output pin for low power mode (for the gate driver). Connect to the LPM pin of the gate driver. Output This pin is an output pin for the low power mode (for the OE1). Connect to the OE1 pin of the gate driver. Timing signal for output, refer to 5.4 Display timing generator. Output This pin is the OE2 output for the gate driver. Connect to the OE2 pin of the gate driver. Timing signal for output, refer to 5.4 Display timing generator. Output This pin is the STB output for the gate driver. Connect to the STVR or STVL pin of the gate driver. Timing signal for output, refer to 5.4 Display timing generator. GCLK CLK output for gate driver RGONG Regulator control 137 134 Output This pin is the CLK output for the gate driver. Connect to the CLK pin of the gate driver. Output Regulator ON/OFF control of gate driver IC Connect to the RGONG pin of the gate driver. 3.4 Power Supply Control Pins Symbol LPMP Pin Name Low power mode signal Pad No. 65 I/O Function This pin connects to LPM pin of power-supply IC. DCON DC/DC converter control 67 Output DC/DC converter ON/OFF signal pin for power-supply IC. This pin connects DCON pin of power-supply IC. RGONP Regulator control 66 Output Regulator ON/OFF control signal pin for power-supply IC. This pin connects to RGONP pin of power-supply IC. VCD11, VCD12 VDD1 booster selection 64, 63 Output Control signal to select x4/x5/x6/x7 booster of power-supply IC for VCC1. Connect to the VCD11 and VCD12 pins of the power-supply IC. VCD2 VDD2 booster selection 62 Output Control signal to select x2/x3 booster of power-supply IC for VCC2. Connect to the VCD2 pin of the power-supply IC. VCE VO level selection 61 Output Signal for selecting the level of the power-supply IC booster voltage, to be used for the maximum voltage of VO. Selects that the booster voltage level is either the same level as VDD1 or a multiple of minus 1. Connect to the VCE pin of the power-supply IC. Output Low power mode control signal output pin (for power-supply IC). 10 Data Sheet S15649EJ2V0DS PD161622 3.5 Driver-Related Pins Symbol S1 to S396 Pin Name Source output Pad No. 556 to 365, 352 to 149 VCOM VCOUT1 COM adjustment Center rectangle signal output VCOUT2 Center rectangle signal output BGRIN External-powersupply connect 90 Input 68 85 81, 82 Output This pin is the common adjustment output. Output This pin is the center rectangle signal output (Vp-p) for common modulation between 0 V to VS. Output This pin is the center rectangle signal output (Vp-p) for common modulation between 0 V to VCC1. This is an external-power-supply connect pin for VCOM. This pin is valid when BGRS (power supply control register 1: R25) = 1. In this case, the reference voltage of the amplifier for setting the common waveform center value is input from outside the PD161622 When BGRS = 0, power supply with built-in the PD161622 is set up as a standard voltage for common waveform center value setup. In this case, leave it open. For more detail, refer to 5.5 Common Adjustment. VCOMR VCOM setting resistor connection 89 Input Connects an external feedback resistor for VCOM setting. This pin is valid when FBRSEL = L. In this case, connect a feedback resistor between the VCOM pin and GND. When FBRSEL = H, the amplifier for setting the common waveform center value operates as a voltage follower. In this case, leave it open. For more detail, refer to 5.5 Common Adjustment. FBRSEL VCOM setting external circuit select 92 Input This pin is used to select the method of adjusting the amplifier for setting the common waveform center value used to set the COMMON drive waveform center level. FBRSEL = H: Voltage follower circuit used (VCOMR connected to VCOM internally) FBRSEL = L: External feedback resistor used CVPH, CVPL, CVNH, CVNL DAC0 to DAC7 D/A converter value setting Basis power supply for -corrected power supplies 77, 76, 75, 74 114 to 107 Input These pins set the reference voltage of the amplifier for setting the VCOM value used to set the COMMON drive waveform center level. These pins are valid when the VCOM output center value setting register (R29) = 00H and BGRS (R25: D6) = 0. This pin is pulled up to the inside IC, therefore, connect to only VSS when in low level setting pin. For more details, refer to 5.5 Common Adjustment Circuit. - This is operational amplifier output pin for the -corrected power supplies. Normally, this pin connects capacitor of 1 F I/O Output Source output pins Function Data Sheet S15649EJ2V0DS 11 PD161622 3.6 Test or Other Pins Symbol TOUT0 to TOUT15, TOSCO TSTRTST, TSTVIHL, TOSCI, TOSCSELI, TOSCSELO, TBSEL1, TBSEL2 TBGR Test input/output COM adjustment Pin Name Source output Pad No. 19 to 4, 26 22, 21, 25, 24, 23, 104, 105 106 I/O This is output pin when PD161622 is in test mode. Normally, leave it open. DUMMY Dummy pin 1 to 3, 86, 87, 139 to 148, 353 to 364, 557 to 562 I/O Function Output This is output pin when PD161622 is in test mode. Normally, leave it open. Output These pins are to set up test mode of PD161622. Normally, fixed it to VSS. - Dummy pin The dummy pins of pads No. 1, 2, 557, and 558 are wired using aluminum inside the PD161622. The dummy pins of pads No. 140, 141, 146, and 147 are wired using aluminum inside the PD161622. 12 Data Sheet S15649EJ2V0DS PD161622 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The I/O circuit types of each pin and recommended connection of unused pins are described below. Power supply VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC1 VCC2 VCC2 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VS VCC1 VS VS VS VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Recommended Connection of Unused Pins Parallel Interface Serial Interface Mode setting pin Always reset on power application Connect to VCC2 (when i80 series interface) Mode setting pin - - - - Register setting pin Connect to VCC1 or VSS. Leave open Input external clock (RSEL = H) Leave open (RSEL = L) Leave open (RSEL = H/L) Leave open Mode setting pin Leave open Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Leave open Always connect to the power IC Always connect to the power IC Always connect to the power IC Always connect to the power IC Always connect to the power IC Leave open Leave open Leave open (BGRS = L [R25]) Leave open (FRBSEL = H) Leave open (FRBSEL = H) Leave open Leave open Connect to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Connect to VSS. Leave open Connect to VCC2 or VSS. Connect to VCC2 or VSS. Leave open Pin Name PSX /RESET /RD (E) C86 D0 to D5 D6 (SCL) D7 (SI) D8 to D15 RS IP0 to IP3 OP0 to OP7 OSCIN OSCOUT CSTB RSEL LPMG GOE1 GOE2 GSTB GCLK RGONG LPMP DCON RGONP VCD11, VCD12 VCD2 VCE VCOUT1 VCOUT2 BGRIN VCOM VCOMR TOUT0 to TOUT15 TOSCO TSTRTST TSTVIHL TOSCI TOSCSELI TOSCSELO TBSEL1 TBSEL2 TBGR Input Type Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger - CMOS CMOS - Schmitt trigger - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O Input Input Input Input I/O I/O I/O I/O Input Input Output Input Output Output Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Input Output Output Input Input Input Input Input Input Input I/O Notes 1 - - 1 - - - - 2 - - - - - 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - Leave open Notes 1. Connect to VCC2 or VSS, depending on the mode selected. 2. Input either H or L by CPU, depending on the register selected 3. Connect to VCC1 or VSS, depending on the mode selected. Data Sheet S15649EJ2V0DS 13 PD161622 5. DESCRIPTION OF FUNCTIONS 5.1 CPU Interface 5.1.1 Selection of interface type The PD161622 chip transfers data using a 16-bit bi-directional data bus (D15 to D0), 8-bit bi-directional data bus (D7 to D0) or a serial data input (SI). Setting the polarity of the PSX pin as either H or L enables the selections shown in table 5-1 below. Table 5-1. PSX H H L X BMD 0 1 Note2 Mode 16-bit parallel 8-bit parallel Serial Note3 /CS /CS /CS /CS RS RS RS RS /RD (E) /RD (E) /RD (E) Note2 /WR (R,/W) /WR (R,/W) /WR (R,/W) Note2 C86 C86 C86 Note2 D15 to D8 D15 to D8 Hi-Z Note1 Note1 D7 D7 D7 SI D6 D6 D6 SCL D5 to D0 D5 to D0 D5 to D0 Hi-Z Note1 Hi-Z Notes 1. Hi-Z: High impedance 2. X: Don't care (1 or 0) 3. In serial mode, read function is not available. 5.1.2 Parallel interface When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection to an i80 series or M68 series CPU (see table 5-2 below). Table 5-2. C86 H L Mode M68 series CPU i80 series CPU /RD (E) E /RD /WR (R,/W) R, /W /WR The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals, as shown in the following table 5-3. Table 5-3. Common RS H H L L M68 series CPU R, /W H L H L i80 series CPU /RD L H L H /WR H L H L Read display data and registers Write display data and registers Prohibited Write to control index register Function 14 Data Sheet S15649EJ2V0DS PD161622 Moreover, when using the parallel interface, it is possible to use the BMD flag (D7 of the data access control register (R5) to select the length of the data to be transmitted as either 16 bits (BMD = 0) or 8 bits (BMD = 1). This setting is valid for the display data written as DR data to the display memory register (R12). The relationship between the command input and the data bus length is as follows. Commands other than those of the display memory register (R12) are executed in 1-byte units regardless of the value of BMD (bus length setting flag in data access control register (R5)). Display memory register (R12) commands are executed in 1-byte units when BMD = 1, and in 1-word units when BMD = 0. (1) Commands other than those of the display memory register (R12) BMD = 1 (8-bit data bus) Pin Data D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 BMD = 0 (16-bit data bus) Pin Data D15 Note D14 Note D13 Note D12 Note D11 Note D10 Note D9 Note D8 Note D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Note 0 or 1 (2) Display memory register (R12) BMD = 1 (8-bit data bus) Pin Data D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 BMD = 0 (16-bit data bus) Pin Data D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Data Sheet S15649EJ2V0DS 15 PD161622 Relationship data bus and display RAM (16-bit parallel interface: BMD = 0) Data bus side 16 bit DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D15 D14 D13 Dot 1 D12 D11 D10 D9 D8 Dot 2 D7 D6 D5 D4 D3 D2 Dot 3 D1 D0 1 pixel (= 1X address) Display RAM side Relationship data bus and display RAM (18-bit parallel interface: BMD = 1) Data bus side 8 bit (1st byte) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 8 bit (2nd byte) DB4 DB3 DB2 DB1 DB0 D15 D14 D13 Dot 1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Dot 3 D1 D0 Dot 2 1 pixel (= 1X address) Display RAM side 16 Data Sheet S15649EJ2V0DS PD161622 Figure 5-1. Example of 16-bit Data Access (i80 series interface, BMD = 0) /CS RS /WR D15 Invalid Invalid Invalid D15 D15 D14 Invalid Invalid Invalid D14 D14 D13 Invalid Invalid Invalid D13 D13 D8 Invalid Invalid Invalid D8 D8 D7 D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D5 D1 D1 D1 D1 D1 D1 D0 D0 1st word (IR) D0 2nd word (DR) D0 1st word (IR) D0 2nd word (DR) Display memory register (R12) D0 3rd word (DR) Registers other than Display memory register (R12) Figure 5-2. Example of 8-bit Data Access (i80 series interface, BMD = 1) /CS RS /WR D15 D7 D7 D7 D15 D7 D15 D6 D6 D6 D6 D14 D6 D14 D5 D5 D5 D5 D13 D5 D13 D1 D1 D1 D1 D9 D1 D9 D0 D0 1st byte (IR) D0 2nd byte (DR) D0 1st byte (IR) D8 2nd byte (DR) D0 3rd byte (DR) D8 4th byte (DR) 2nd pixel date Registers other than Display memory register (R12) 1st pixel date Display memory register (R12) Data Sheet S15649EJ2V0DS 17 PD161622 (1) i80 Series Parallel Interface When i80 series parallel data transfer has been selected, data is written to the PD161622 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-3. i80 Series Interface Data Bus Status /CS /WR /RD Hi-Z DBn Data write Valid data Data read Hi-Z (2) M68 Series Parallel Interface When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal. Figure 5-4. M68 Series Interface Data Bus Status (when data read) /CS R,/W E Hi-Z Hi-Z DBn Valid data Hi-Z 18 Data Sheet S15649EJ2V0DS PD161622 5.1.3 Serial interface When the serial interface has been selected (PSX = L), if the chip is active (/CS = L), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to parallel data for processing. RS input is used to judge serial input data as display data or command data when RS = H the data is display data and when RS = L the data is command data. When the chip enters active mode, RS input is read at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is shown below. Figure 5-5. Serial Interface Signal Chart /CS SI SCL RS D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings. 2. The data read function is disabled during serial interface mode. 3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from external sources. Our recommends checking operation with the actual device. 5.1.4 Chip select The PD161622 has two chip select pins (/CS). The CPU parallel and serial interfaces can be used only when /CS = L. When the chip select pin is inactive, D0 to D15 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. If a serial interface mode has been set, the shift register and counter are both initialized. Data Sheet S15649EJ2V0DS 19 PD161622 5.1.5 Access to display data RAM and internal registers When the CPU accessed the PD161622, the CPU only has to satisfy the requirement of the cycle time (tCYC) and can transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration. A high-speed RAM write function, as well as the ordinary RAM write function, is provided for writing data to the display data RAM. By using the high-speed write function, data can be written to the display RAM at an access speed four times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. For details, refer to 5.2.5 High-speed RAM write mode Dummy data is not required when either reading or writing data. In the PD161622, data of the display memory register (R12) cannot be read. This relationship is shown in Figure 5-6. Note that when in write mode of data at high speed for data read mode of read cycle time, this mode equals to normal mode. Figure 5-6. Image of internal access to display RAM Writing /WR DATA n n+1 n+2 n+3 Reading (display memory register) /WR /RD DATA n Dummy n n+1 Reading (registers other than display memory register) /WR /RD IRn Data DATA IRn n n+1 IR Address Set #n IRn Register Data Read IR Address Set #n+1 IRn+1 Register Data Read 20 Data Sheet S15649EJ2V0DS PD161622 5.2 Display Data RAM This RAM stores dot data for display and consists of 2,112 bits (132 x 16) x 176 bits. Any address of this RAM can be accessed by specifying an X address and an Y address. Display data D0 to D15 transmitted from the CPU corresponds to the pixels on the LCD (refer to Table 5-5). Table 5-5. Display Data RAM D15 D14 D13 Dot 1 D12 D11 D10 D9 D8 Dot 2 Pixel 1 (= 1 x address) D7 D6 D5 D4 D3 D2 Dot 3 D1 D0 5.2.1 X address circuit An X address of the display data RAM is specified by using the X address register as shown in Figure 5-8. If the X address increment mode (INC = 0: data access control register: R5) is used, the specified X address is incremented or decremented by one each time display data is written. Whether the address is incremented or decremented is specified by the XDIR flag of data access control register (R5) as shown in Table 5-6. In the increment mode, the X address is incremented up to 83H. If more display data is written, the Y address is incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 00H. In the decrement mode, the X address is decremented to 00H. If more display data is written, the Y address is incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 83H. 5.2.2 Y address circuit A Y address of the display data RAM is specified by using the Y address register as shown in Figure 5-8. If the Y address increment mode (INC = 1: data access control register: R5) is used, the specified Y address is incremented or decremented by one each time display is written. Whether the address is incremented or decremented is specified by the YDIR flag of data access control register (R5) as shown in Table 5-6. In the increment mode, the Y address is incremented up to AFH. If more display data is written, the X address is incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 00H. In the decrement mode, the Y address is decremented to 00H. If more display data is written, the X address is incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to AFH. The relationship between the setting of INC, XDIR, and YDIR of data access control register (R5) and the address is as follows: Data Sheet S15649EJ2V0DS 21 PD161622 Table 5-6. Data Access Control Register (R5) Setting INC 0 1 Setting The address is successively incremented or decremented in the X direction when data is accessed. The address is successively incremented or decremented in the Y direction when data is accessed. XDIR 0 1 YDIR 0 1 Setting Increments the X address (+1) when data is accessed. Decrements the X address (-1) when data is accessed. Setting Increments the Y address (+1) when data is accessed. Decrements the Y address (-1) when data is accessed. Table 5-7. Combination of INC, XDIR, and YDIR, and Address Direction INC 0 XDIR 0 0 1 1 1 0 0 1 1 YDIR 0 1 0 1 0 1 0 1 Image of Address Scanning A-1 A-2 A-3 A-4 B-1 B-2 B-3 B-4 Caution If the access direction is changed by using INC, XDIR, or YDIR, be sure to set the X address register (R6) and Y address register (R7) before accessing the display RAM. 22 Data Sheet S15649EJ2V0DS PD161622 Figure 5-7. Combination of INC, XDIR, and YDIR, and Address Scanning Image 00H A-1 X address 83H 00H A-3 A-4 AFH 00H X address 83H 00H B-1 B-2 B-3 B-4 AFH 5.2.3 Column address circuit When the contents of the display data RAM are displayed, column addresses are output to the SEG output pins as shown in Figure 5-8. The correspondence relationship between the column addresses of the display RAM and segment outputs can be reversed by the ADC flag (segment driver direction select flag) of control register 1 (R0) as shown in Table 5-8. This reduces the restrictions on chip layout when the LCD module is assembled. Table 5-8. Relationship between Column Address of Display RAM and Segment Output SEG Output ADC 0 1 SEG1 000H 18BH SEG2 000H 18AH Column address Column address SEG385 18AH 001H SEG386 18BH 000H Data Sheet S15649EJ2V0DS Y address Y address A-2 23 PD161622 Figure 5-8. PD161622 RAM Addressing Source output ADC=0 ADC=1 X-address Column addres S1 S396 000H D15---D11 S2 S395 000H 001H D10---D5 S3 S394 002H D4---D0 S4 S393 003H D15---D11 S5 S392 001H 004H D10---D5 Y6 S391 005H D4---D0 --------- --------- S391 S6 186H D15---D11 S392 S5 08EH 187H D10---D5 S393 S4 188H D4---D0 S394 S3 189H D15---D11 S395 S2 08FH 18AH D10---D5 S396 S1 18BH D4---D0 Gate output R,/L=H R,/L=L O1 O2 | | O87 O88 O89 O90 | | O175 O176 O176 O175 | | O90 O89 O88 O87 | | O2 O1 Y-address 00H 01H | | 56H 57H 58H 59H | | AEH AFH Display area 24 Data Sheet S15649EJ2V0DS PD161622 5.2.4 Arbitrary address area access (window access mode (WAS)) With the PD161622, any area of the display RAM selected by the MIN.*X/Y address registers (R8 and R10) and MAX. X/Y address registers (R9 and R11) can be accessed. A setup of data access control (R5): WAS = 1 chooses window access mode. And PD161622 accesses only the domain set up by MIN. X/Y address registers and MAX. X/Y address registers. The address scanning setting by INC, XDIR, and YDIR of data access control register (R5) is also valid in window access mode, in the same manner as when data is normally written to the display RAM. In addition, data can be written from any address by specifying the X address register (R6) and Y address register (R7). Note that the display RAM must be accessed after setting the X address register (R6) and Y address register (R7) if the window access area has been set or changed by the MIN. X/Y address register or MAX. X/Y address register. Figure 5-9. Example of Incrementing Address When INC = 0, XDIR = 0, and YDIR = 0 MIN. . X address Start point 00H MAX. . X address 83H 00H MIN. . Y address . . . MAX. . Y address AFH End point Cautions 1. When using the window access mode, the relationship between the start point and end point shown in the table below must be established. Item X address Y address Address Relation Ship 00H MIN.X address X address (R4) MAX.X address 83H 00H MIN.Y address Y address (R5) MAX.Y address AFH 2. If invalid address data is set as the MIN./MAX.address, operation is not guaranteed. 3. Do not specify any value other than the address value 4n-n (n = 1 to 33) for the X address in the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set. 4. Access the display RAM after setting the X address register (R6) and Y address register (R7) if the window access area has been set or changed by the MIN. X/Y address register or MAX. X/Y address register. Data Sheet S15649EJ2V0DS 25 PD161622 Figure 5-10. Example of Sequence in Window Access Mode Start Data access control register (R5) (WAS = 1) Sets window access mode. MIN. . X address register (R8) Sets start point. MIN. . Y address register (R10) MAX. . X address register (R9) Sets end point. MAX. . Y address register (R11) X address register (R6) Y address register (R7) Display memory register (R12) Data No Writing complete? Yes End 26 Data Sheet S15649EJ2V0DS PD161622 5.2.5 High-speed RAM write mode With the PD161622, two types of access modes can be selected for accessing the display RAM. The PD161622 has a high-speed RAM write function, as well as an ordinary RAM write function. By using the highspeed write function, data can be written to the display RAM at an access speed four times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display where the display data must be rewritten at high speeds, can be supported. When the high-speed RAM write mode is selected by using BSTR of the data access control register (R5), data is temporarily stored in an internal register of the PD161622. When data of 64 bits (16 bits x 4) has been stored in the register, it is written to the display RAM. It is also possible to write the next data to the internal register while the first data is being written to the RAM. In the high-speed RAM write mode, however, the CPU must transmit data in units of 64 bits (4 pixels) have been written to the internal register. If data of less than 64 bits is transmitted in the high-speed RAM write mode, this data is not written to the display RAM. Therefore, CPU data is not reflected on the LCD display even if it is transmitted. In this case, the data that is not reflected remains stored in the register. When the next data is transmitted, it is written to the register from where the preceding data is stored. However, if the chip select signal is disserted inactive (/CS = H) in the middle of data transfer, and then asserted active again and when the display data register (R12) is set, the register is initialized. Consequently, the data stored in the register is lost. It is therefore recommended to transmit display data in 64-bit units when using the high-speed RAM write mode. Figure 5-11. Image of Operation in High-speed Write Mode Display RAM 64-bit 64-bit 64-bit 64 64 64-bit register 64 64 8/16 8/16 8/16 Display Data 8/16 Parallel / Serial Interface circuit Caution Do not specify any value other than the address value 4n-n (n = 1 to 33) for the X address (R6) in the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set. Data Sheet S15649EJ2V0DS 27 PD161622 Figure 5-12. Example of Sequence in High-Speed RAM Write Mode (with 16-Bit Parallel Interface) Start High speed RAM write mode setting (R5: BSTR[D6] = 1) Sets the high-speed RAM write mode. X address setting register (R6)Note Y address setting register (R7) Display memory register (R12) 1st word (4n - 4) display data (16 bit) 2nd word (4n - 3) display data (16 bit) 3rd word (4n - 2) display data (16 bit) 4th word (4n - 1) display data (16 bit) No Data write sequence (writing data in 64-bit units) End of data Yes Next processing End n: n 1 Note Do not specify any value other than the address value 4n-n (n = 1 to 33) for the X address (R6) in the high-speed RAM access mode. The operation is not guaranteed if invalid address data is set. 28 Data Sheet S15649EJ2V0DS PD161622 5.3 Oscillator The PD161622 has a CR oscillator (with external R), which generate the display clock. When RSEL is L, an internal CR oscillator is selected. Leave both OSCIN pin and OSCOUT open. When RSEL is H, an external oscillator is selected. Connect 51 k resistance between OSCIN and OCSOUT pin. This oscillator also has a calibration function, which is available by itself to set the number of frame frequency of display driving. Frame frequency calibration is set by calibration register (R45). The time to select one line is set by the calibration start and stop commands. Figure 5-13. Frame Frequency Calibration Calibration command Start/Stop Register OSC n-bit counter Internal clock The calibration function involves counting the number of oscillation clocks generated between the start and stop signals and storing that number in a register. The number of oscillation clocks is then continually compared with this register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line selection time, and used as the internal reference clock. Using the time to set calibration (tcal) can be selected either tcal or tcal x 2 through control register (R1): LTS. Figure 5-14. Calibration Function Timing (LTS [R1] = 0) Calibration start tcal (1 line time) Calibration stop tcal = 1/(fFRAME x n) fFRAME = Frame frequency n: Line numbers 1 OSC1 2 3 4 5 6 7 1 OSC2 2 3 4 Data Sheet S15649EJ2V0DS 29 PD161622 5.4 Display Timing Generator 5.4.1 Drive timing The PD161622 generates the TFT-LCD drive timing inside the PD161622. The TFT-LCD panel is driven at the timing of one line selection period generated based on the calibration time (tcal) set by the calibration function, as shown in the figure below. One line selection period is made up of a pre-charge period, a source output period, and the PD161622 output control clock. The pre-charge and source output periods are set by the pre-charge period setting register (R46) and calibration register (R45), respectively, based on the following expressions. 1 line selection period = tcal Pre-charge period = tpr Source output period = tsout tcal: Calibration setting time [R45] tpr = (1/fOSC) x (CLKpr + 2 CLK) tsout = tcal - (tpr + 3 CLK) CLKcal: Calibration setting time (tcal) clock number = tcal / (1fOSC) CLKpr: Pre-charge peiod setting register clock number [R46: PLIMn] n 1 CLK = 1/fOSC fOSC: Oscillator frequency 30 Data Sheet S15649EJ2V0DS PD161622 Figure 5-15. 1-line Select Time 1 line select time 1 CLK fOSC Output control basis clock 1 0 1 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 3 4 5 6 Pre-charge time: tpr 2 CLK Source output time: tsout 2 CLK CLKpr CLsout 4 CLK Sn GCLK GSTB GOE1 Gn VCOUT Data Sheet S15649EJ2V0DS 31 PD161622 The display timing generator generates the timing signals for the internal timing of the source driver and for the gate driver. The output timings for normal operation, for normal operation stand-by mode, and for stand-by mode normal operation, are shown below. Figure 5-16. During Normal Operation (during line inversion) GSTB Data output line no. GCLK GOE1 176 dummy 1 2 3 4 5 176 dummy 1 2 GOE2 Sn VCOUT G176 G1 G2 G3 32 Data Sheet S15649EJ2V0DS PD161622 Figure 5-17. Normal Operation Stand-by Input (during line inversion) (1) (2) GSTB Data output line no. GCLK GOE1 176 dummy 1 2 3 4 5 176 dummy GOE2 Sn VCOUT G176 G1 G2 G3 G4 Stand-by command input Stand-by mode start Stand-by statement Data Sheet S15649EJ2V0DS 33 PD161622 Figure 5-18. Normal Operation Stand-by Input (during line inversion) (1) Reference 1 line select time (3 line) 1 CLK 1 line select time (4 line) fOSC GSTB GCLK GOE1 GOE2 Sn VSS G2 G3 G4 VCOUT VSS Stand-by command Stand-by mode start 34 Data Sheet S15649EJ2V0DS PD161622 Figure 5-19. Normal Operation Stand-by Input (during line inversion) (2) Reference Stand-by time 1 line select time (dummy line) 1 CLK fOSC Oscillation stop GSTB GCLK GOE1 GOE2 Sn VSS G176 G3 G4 All gate on VCOUT VSS Stand-by command Data Sheet S15649EJ2V0DS 35 PD161622 Figure 5-20. Stand-by Return to Normal Operation (during line inversion) GSTB Data output line no. GCLK GOE1 dummy 1 2 3 4 5 GOE2 Sn VCOUT G176 G1 G2 G3 G4 Stand-by release command input 36 Data Sheet S15649EJ2V0DS PD161622 5.5 Common Adjustment Circuit To generate common output, the center voltage of the common waveform is output from the VCOM pin along with output of a 0 to VS (V) square waveform from the VCOUT1 pin and 0 to VCC1 (V) from VCOUT2. The level of the VCOM output can be adjusted using as external resistor. Figure 5-21. Common Adjustment Circuit R29 VS R25 (PVCOM) D/A converter R25 (BGRS) VBGR Rectangle waveform value VCOUT1: Vp-p = VS VCOUT2: Vp-p = VCC1 BGRIN DAC7 DAC0 VCOMR FBRSEL VCOM VCOUT1, VCOUT2 R1 R3 R2 C1 VCOMMON VS, VCC1 0V VCOMMON waveform center setting The VCOM voltage formulas are shown below. Data Sheet S15649EJ2V0DS 37 PD161622 5.6 Rectangular Signal Generator This circuit generates a common rectangular signal. A rectangular wave of 0 to VS (V) is output from the VCOUT1 pin, and a wave of 0 to VCC1 (V) is output from the VCOUT2 pin. The common output wave necessary for driving an LCD can be generated by connecting an external circuit as shown in Figure 5-21. 5.7 Reference Voltage Generator (VBGR) The PD161622 has a reference voltage generator for the voltage regulator. This reference voltage generator generates a constant voltage from VCC1. The constant voltage generated by this circuit is connected to the input of the operational amplifier that adjusts the center level of the COMMON drive output, via a D/A converter. By using this voltage, therefore, the center level of the COMMON drive output can be kept constant, without being affected by fluctuations in the supply voltage. The common output waveform necessary for driving an LCD can be generated by connecting the external circuit show in Figure 5-21. When the internal reference voltage generator is not used (R25: BGRS = 1), directly input the reference voltage to the operational amplifier that adjusts the center level of the COMMON drive output. 5.8 D/A Converter Circuit The PD161622 is provided with an internal D/A converter to adjust the voltage of the reference voltage generator for the voltage regulator. This D/A converter divides the constant voltage generated by the reference voltage generator (VBFR) by 256, and a level of voltage between VBGR and VSS can be selected by setting the VCOM electronic volume register (R29). In addition, this D/A converter also has a function to select a level by using an external pin. If the set value of the VCOM electronic volume register (R29) is 00H, the set statuses of the DAC7 to DAC0 pins are valid. When DACn pin input is valid (R29 = 00H), these pins are pulled up internally , so only the pins that are to be set to L should be connected to VSS. Table 5-9. Setting of VCOM Electronic Volume Register (R25: BGRS = 0) EV7 DAC7 00H 01H 02H 03H FEH FFH 1 1 1 1 1 1 0 0 0 0 EV6 DAC6 0 0 0 0 EV5 DAC5 0 0 0 0 EV4 DAC4 0 0 0 0 1 1 1 1 1 1 1 1 0 1 EV3 DAC3 0 0 0 0 EV2 DAC2 0 0 0 0 EV1 DAC1 0 0 1 1 EV0 DAC0 0 1 0 1 DACn set value 0 2 3 4 255 256 DACn Remark R29 38 Data Sheet S15649EJ2V0DS PD161622 5.9 -Curve Correction Power Supply Circuit The PD161622 includes a -curve correction power supply circuit. If the internal -curve correction matches the LCD characteristics, no external components are necessary. This power circuit has white level and black level reference voltage generators on the positive and negative polarity sides, and also supports unbalanced driving. The reference voltage generators consist of a D/A converter and an operational amplifier and divide VS to VSS by 256. One level of voltage can be selected by using the contrast value setting registers (R36 to R39) Figure 5-22. -Curve Correction Circuit VS SPH2 SR36 custom SNL2 VSS SPH1 V0 VRH D/A (R36) VPH D/A (R37) VNH SR37 00H : SW ON AMP OFF SNL1 SNH1 V5 D/A (R38) VPL SPL1 VRL1 D/A (R39) VNL SNH2 SPL2 VRL2 VSS Data Sheet S15649EJ2V0DS SR39 00H : SW ON AMP OFF SR38 VS 39 PD161622 Figure 5-23. Relationship of TFT Drive Voltage (normally white) VS VPH VNH Black VPL VNL VSS Positive polarity Negative polarity White Drive level VPH VNH VPL VNL Positive polarity, black Negative polarity, white Positive polarity, black Negative polarity, white Setting register Contrast value setting register 1 Contrast value setting register 2 Contrast value setting register 3 Contrast value setting register 4 R36 R37 R38 R39 The value of each amplifier output can be expressed as follows and the value of can be set as shown in Table 5- 10 and 5-11by using the contrast value registers (R36 to R39) VNL, BVPL, VNH, VPH = ( / 256) x VS Caution The usable range in which each output level of VPH, VNH, VPL, and VNL can be set depends on the -curve. Table 5-10. -Contrast Value Setting and Electronic Volume Register Setting 1 (VPH, VNL) R36 R37 00H 01H 02H 03H FEH FFH 1 1 1 1 1 1 GPH7 GNH7 0 0 0 0 GPH6 GNH6 0 0 0 0 GPH5 GNH5 0 0 0 0 GPH4 GNH4 0 0 0 0 1 1 1 1 1 1 1 1 0 1 GPH3 GNH3 0 0 0 0 GPH2 GNH2 0 0 0 0 GPH1 GNH1 0 0 1 1 GPH0 GNH0 0 1 0 1 value setting or status setting Fixed to VS (amplifier OFF) 255 254 253 2 1 40 Data Sheet S15649EJ2V0DS PD161622 Table 5-11. -Contrast Value Setting and Electronic Volume Register Setting 1 (VPL, VNL) R36 R37 00H 01H 02H 03H FEH FFH 1 1 1 1 1 1 GPL7 GNL7 0 0 0 0 GPL6 GNL6 0 0 0 0 GPL5 GNL5 0 0 0 0 GPL4 GNL4 0 0 0 0 1 1 1 1 1 1 1 1 0 1 GPL3 GNL3 0 0 0 0 GPL2 GNL2 0 0 0 0 GPL1 GNL1 0 0 1 1 GPL0 GNL0 0 1 0 1 value setting or Statement setting Fixed to VS (amplifier OFF) 255 254 253 2 1 Relationship between Setting Value of R36 to R39 Registers and Switch Status (GSEL[R1] = 1) Register R36 R37 R38 R39 Setting value 00H Other than 00H 00H Other than 00H 00H Other than 00H 00H Other than 00H SR36 SR37 SR38 SR39 Switch Status ON OFF ON OFF ON OFF ON OFF Amplifier OFF ON OFF ON OFF ON OFF ON The relationship between the setting of the contrast value setting register and the driven waveform is explained next, taking the -curve in Figure 5-22 as an example. Table 5-12. Switch Status when -Curve Correction Power Supply Circuit is not used (GSEL[R1] = 0) Polarity Positive Negative Switch status SPH1 x x SNL1 x x SNH1 x x SPL1 x x SPH2 ON OFF SNL2 OFF ON SNH2 OFF ON SPL2 ON OFF Remark x: Switch is normally OFF with the amplifier OFF. Relationship of drive voltage (normally white) VS VPH VNH Black VPL VNL VSS Positive polarity Negative polarity White Data Sheet S15649EJ2V0DS 41 PD161622 Table 5-13. Switch Status when -Curve Correction Power Circuit is used (GSEL[R1] = 1) Polarity Positive Negative Switch status SPH1 ON OFF SNL1 OFF ON SNH1 OFF ON SPL1 ON OFF SPH2 x x SNL2 x x SNH2 x x SPL2 x x Remark x: Switch is normally OFF Relationship of drive voltage (normally white) VS VPH VNH Black VPL VNL VSS Positive polarity Negative polarity White 42 Data Sheet S15649EJ2V0DS PD161622 Figure 5-24. TFT Drive Voltage Level VS SR36 SPH2 SNL2 VSS SPH1 V0 VRH D/A (R36) VPH SR37 00H : SW ON AMP OFF D/A (R37) VNH SNL1 SNH1 D/A (R38) VPL SPL1 VRL1 D/A (R39) VNL SNH2 SPL2 VRL2 VSS Data Sheet S15649EJ2V0DS SR39 00H : SW ON AMP OFF SR38 VS Drive voltage range V5 43 PD161622 Table 5-14. -Curve Correction Circuit (-correction resistance) Display Data D10 - D5 D15 - D11, D4 - D0 00H 00H 01H - 02H - 03H 01H 04H - 05H 02H 06H - 07H 03H 08H - 09H 04H 0AH - 0BH 05H 0CH - 0DH 06H 0EH - 0FH 07H 10H - 11H 08H 12H - 13H 09H 14H - 15H 0AH 16H - 17H 0BH 18H - 19H 0CH 1AH - 1BH 0DH 1CH - 1DH 0EH 1EH - 1FH 0FH 20H - 21H 10H 22H - 23H 11H 24H - 25H 12H 26H - 27H 13H 28H - 29H 14H 2AH - 2BH 15H 2CH - 2DH 16H 2EH - 2FH 17H 30H - 31H 18H 32H - 33H 19H 34H - 35H 1AH 36H - 37H 1BH 38H - 39H 1CH 3AH - 3BH 1DH 3CH - 3DH 1EH 3EH - 3FH 1FH Total Resistance (k) 1 1.587 2 1.226 3 2.453 4 3.390 5 4.112 6 4.905 7 1.731 8 1.443 9 1.587 10 1.515 11 1.082 12 1.082 13 1.154 14 1.226 15 1.298 16 1.082 17 0.649 18 0.721 19 0.794 20 0.721 21 0.794 22 0.505 23 0.577 24 0.577 25 0.577 26 0.505 27 0.433 28 0.433 29 0.433 30 0.433 31 0.505 32 0.361 33 0.433 34 0.433 35 0.433 36 0.433 37 0.433 38 0.433 39 0.505 40 0.433 41 0.433 42 0.433 43 0.505 44 0.361 45 0.433 46 0.433 47 0.361 48 0.361 49 0.361 50 0.361 51 0.433 52 0.433 53 0.433 54 0.505 55 0.505 56 0.505 57 0.721 58 0.721 59 0.866 60 0.866 61 1.587 62 2.597 63 2.597 64 12.047 65 7.719 80.000 Output Voltage (V) Positive Voltage Negative Voltage 4.901 0.107 4.824 0.190 4.671 0.356 4.459 0.586 4.202 0.864 3.895 1.196 3.787 1.313 3.697 1.411 3.598 1.519 3.503 1.621 3.436 1.694 3.368 1.768 3.296 1.846 3.219 1.929 3.138 2.017 3.070 2.090 3.030 2.134 2.985 2.183 2.935 2.236 2.890 2.285 2.840 2.339 2.809 2.373 2.773 2.412 2.737 2.451 2.701 2.490 2.669 2.524 2.642 2.554 2.615 2.583 2.588 2.612 2.561 2.642 2.529 2.676 2.507 2.700 2.480 2.729 2.453 2.759 2.426 2.788 2.399 2.817 2.372 2.847 2.344 2.876 2.313 2.910 2.286 2.939 2.259 2.969 2.232 2.998 2.200 3.032 2.178 3.057 2.151 3.086 2.124 3.115 2.101 3.140 2.078 3.164 2.056 3.188 2.033 3.213 2.006 3.242 1.979 3.271 1.952 3.301 1.921 3.335 1.889 3.369 1.858 3.403 1.812 3.452 1.767 3.501 1.713 3.560 1.659 3.618 1.560 3.726 1.398 3.901 1.235 4.077 0.482 4.893 Gray scale 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r 44 Data Sheet S15649EJ2V0DS PD161622 Figure 5-25. -Curve Corrected Circuit (-corrected resistance value) 5.000 4.000 Level voltage [V] 3.000 2.000 1.000 0.000 0 10 20 30 Gray scale level Positive Voltage Negative Voltage 40 50 60 Data Sheet S15649EJ2V0DS 45 PD161622 Figure 5-26. Internal Connection of V0 to V5, VRH, VRL1, and VRL2 -correction resister VS SPH2 SNL2 VSS VPH SPH1 r1 V0 r2 r16 V2 r17 SNL1 VRH r6 V1 r7 VNH SNH1 r63 V5 VPL SPL1 r64 VRL1 r50 V3 r51 r60 V4 VNL r65 SNH2 VS SPL2 VRL2 VSS r61 46 Data Sheet S15649EJ2V0DS PD161622 5.10 Partial Display Mode The PD161622 is provided with a function that allows sections within the screen to be displayed separately (partial display mode). The start line of the area to be displayed in partial display mode is set using the partial display area start line register (R20, R21), the number of lines in the area to be displayed is set using the partial display area line count register (R22, R23), and the color of the area not to be displayed is set using the partial off area color register (R19). If "1" is set in the partial display area line count registers (R22, R23), the partial display areas each become 1 line. If "0" is set, there are no partial display areas but only normal display areas. The non-display area indicated by R20 and R22 is called Partial 1, and the non-display area indicates by R21 and R23 is called Partial 2. The Partial 2 setting is enabled only when the Partial 1 setting has been performed (when R22 0). Therefore, to set only one area as a non-display area, perform only the setting for Partial 1. Low power consumption cannot be achieved if only the partial mode is set. If low power consumption is required, the mode must be switched to the 8-clor mode. Figure 5-26. Partial Display Mode 00H 01H 02H 03H ... 81H 82H 83H Display start line (00H) Partial display start line (R20, R21) Partial display area line number(R22, R23) Section not displayed Cautions 1. The "scroll step count register (R17)" command is ignored in the partial display mode. 2. The specified partial areas must not directly overlap, and the Partial 1 area and Partial 2 area must be separated by at least one line. If the areas overlap, only the Partial 1 settings are valid, and partial display is not performed for the Partial 2 area. 3. When setting the partial display areas, be sure to observe the following relationship. "00H" R20 (R21) R22 (R23) "AFH" The following sequence is recommended to avoid display malfunction when switching from normal display mode to partial display mode and vice versa. Data Sheet S15649EJ2V0DS 47 PD161622 (1) Recommended sequence for switching from normal display mode to partial display mode DISP1 = 1 or DISP1 = 0, DISP0 = 1 R0 D7 D2 <1> Display off PGDn setting Display data overwrite (for partial display) R19 D0 <2> Partial off area color register setting Note1 <3> Display data overwrite Note1 D7 P1SLn, P2SLn setting R20, R21 <4> Partial display area start line setting Note1 D0 D7 P1AWn, P2AWn setting DTY = 1, COLOR = 1 DISP1 = 0, DISP0 = 0 R22, R23 R0 R0 <5> Partial display area line count setting Note1 D0 D4, D2 D7 <6> Partial display mode, 8-color mode Note2 <7> Display on Notes 1. <2> to <5> can be executed in any order. 2. <6> must be executed after <4> and <5> have been set. 48 Data Sheet S15649EJ2V0DS PD161622 (2) Recommended sequence for switching from partial display mode to normal display mode DISP1 = 1 or DISP1 = 0, DISP0 = 1 Display data overwrite (for normal display) DTY = 0, COLOR = 0 DISP1 = 0, DISP0 = 0 R0 D7 <1> Display off <2> Display data overwrite Note R0 R0 D4, D2 D7 <3> Partial display mode, 65,000-color mode Note <4> Display on Note <2> to <3> can be executed in any order. (3) Recommended sequence for switching from partial display mode to partial display mode (switching the partial display area) DISP1 = 1 or DISP1 = 0, DISP0 = 1 (display data overwrite) R0 D7 <1> Display off <2> Display data overwrite Notes Note1, 2 D7 P1SLn, P2SLn setting R20, R21 <3> Partial display area start line setting Note1 D0 D7 P1AWn, P2AWn setting DTY = 1 DISP1 = 0, DISP0 = 0 R22, R23 R0 R0 <4> Partial display area line count setting Note1 D0 D4 D7 <5> Partial display mode Note3 <6> Display on Notes 1. <2> to <4> can be executed in any order. 2. Execute <2> only when necessary. 3. <5> must be executed after <3> and <4> have been set. Data Sheet S15649EJ2V0DS 49 PD161622 (4) Partial display setting examples Setting A-1 Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 00H 58H Details of Setting Value Sets Y address 00H Sets an area of 88 lines Setting A-2 Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 58H 58H Details of Setting Value Sets Y address 58H Sets an area of 88 lines Setting A-3 Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 84H 58H Details of Setting Value Sets Y address 84H Sets an area of 88 lines Setting A-4 Register Partial display area start line register (R20, R21) Partial display area line count register (R22, R23) Setting Value 2CH 58H Details of Setting Value Sets Y address 2CH Sets an area of 88 lines 50 Data Sheet S15649EJ2V0DS PD161622 Figure 5-28. Partial Display Setting Examples Setting A-1 132 Gate 1 Source Gate 1 1 Source 1 Setting A-2 132 Partial display area Area not displayed 88 89 88 89 Area not displayed Partial display area 176 176 Source Gate 1 1 Setting A-3 132 Partial display area Gate Source 1 1 Setting A-4 132 Area not displayed 44 45 44 45 Area not displayed Partial display area 132 133 Partial display area 176 132 133 Area not displayed 176 Data Sheet S15649EJ2V0DS 51 PD161622 5.11 Screen Scroll The PD161622 has a screen scroll function. Any area of the screen can be scrolled by using the scroll area start line register (R15), scroll area line count register (R16), and scroll step count register (R17) to set the Y address of the top line of the area to be scrolled, the count of lines of the area to be scrolled, and the scroll step number, respectively. Note that in partial mode, the screen scroll function is disabled. Table 5-15. Scroll Area Start Line Register (R15) SSL7 0 0 0 0 1 1 1 SSL6 0 0 0 0 0 0 0 SSL5 0 0 0 0 1 1 1 SSL4 0 0 0 0 0 0 0 SSL3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SSL2 0 0 0 0 SSL1 0 0 1 1 SSL0 0 1 0 1 Start Line Y Address 00H 01H 02H 03H ADH AEH AFH Table 5-16. Scroll Area Line Count Register (R16) SAW7 0 0 0 0 1 1 1 SAW6 0 0 0 0 0 0 0 SAW5 0 0 0 0 1 1 1 SAW4 0 0 0 0 0 0 0 SAW3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SAW2 0 0 0 0 SAW1 0 0 1 1 SAW0 0 1 0 1 Scroll Area Line Number 1 2 3 4 174 175 176 Table 5-17. Scroll Step Count Register (R17) SST7 0 0 0 0 1 1 1 SST6 0 0 0 0 0 0 0 SST5 0 0 0 0 1 1 1 SST4 0 0 0 0 0 0 0 SST3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SST2 0 0 0 0 SST1 0 0 1 1 SST0 0 1 0 1 Scroll Step Number 0 (no scroll) 1 2 3 173 174 175 Scrolling must be set using the following sequence. 52 Data Sheet S15649EJ2V0DS PD161622 (1) Recommended scroll sequence D7 SSLn setting R15 D0 D7 <1> Scroll area start line setting Note1 SAWn setting R16 D0 D7 <2> Scroll area line count setting Note1 SSTn setting R17 D0 <3> Scroll step count register setting Note2 Notes 1. <1> to <2> can be executed in any order. 2. <3> must be executed after <1> and <2> have been set. Remark Set SSTn to 00H to disable the scroll operation. No particular sequence is required for this. Cautions 1. If the sum of the values of SSLn and SAWn is 176 (AFH) or over, it is invalid (no scroll operation). 2. Set the step number SSTn so that it does not exceed the line number SAWn. If a value exceeding SAWn is set, it will be invalid (no scroll operation). Data Sheet S15649EJ2V0DS 53 PD161622 (2) Scroll setting examples Setting A-1 Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 00H AFH Details of Setting Value Sets Y address 00H Sets an area of 176 lines Setting A-2 Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 00H 57H Details of Setting Value Sets Y address 00H Sets an area of 88 lines Setting A-3 Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 58H 57H Details of Setting Value Sets Y address 58H Sets an area of 88 lines Setting A-4 Register Scroll area start line register (R15) Scroll area line count register (R16) Setting Value 2CH 57H Details of Setting Value Sets Y address 2CH Sets an area of 88 lines 54 Data Sheet S15649EJ2V0DS PD161622 Figure 5-29. Display Scroll Setting Examples Setting A-1 132 Gate 1 Source Gate 1 1 Source 1 Setting A-2 132 Scroll area Scroll area 88 89 Fixed display area 176 176 Source Gate 1 1 Setting A-3 132 Gate Source 1 1 Setting A-4 132 Fixed display area 44 45 Fixed display area 88 89 Scroll area Scroll area 132 133 Fixed display area 176 176 Data Sheet S15649EJ2V0DS 55 PD161622 (3) Scroll setting flowchart example Start Scroll area start line register assignment Scroll area start line register setting Scroll area line count register assignment Scroll area line count register setting IR Scroll step count register assignment Scroll step count register setting (1 step) IR X address register assignment R6 X address register setting IR Y address register assignment R7 Y address register setting D7 to D0 Y address register RS MSB LSB IR D6 to D0 Index register RS MSB LSB L R15 X 0 0 0 1 1 1 1 D7 to D0 Scroll area start line register RS MSB LSB H IR D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are the data for Scroll area start line. D5 to D0 Index register RS MSB LSB L R16 X 0 0 1 0 0 0 0 D7 to D0 Scroll area line count register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are the data for Scroll area line count register. D6 to D0 Index register RS MSB LSB L R17 X 0 0 1 0 0 0 1 D7 to D0 Scroll step count register RS MSB LSB H 0 0 0 0 0 0 0 1 D6 to D0 Index register RS MSB LSB L X 0 0 0 0 1 1 0 D7 to D0 X address register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 depend on application condition. D6 to D0 Index register RS MSB LSB L X 0 0 0 0 1 1 1 H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 depend on application condition. 56 Data Sheet S15649EJ2V0DS PD161622 IR Display memory assignment Display data Re-write scrolling area 1 (start) Display data Re-write scrolling area 2 Display data Re-write scrolling area n (end) IR Scroll step count register assignment R17 Scroll step count register setting (2 steps) IR X address register assignment R6 X address register setting IR Y address register assignment R70 Y address register setting IR Display memory assignment D7 to D0 Y address register RS MSB LSB D6 to D0 Index register RS MSB LSB L R12 X 0 0 0 1 1 0 0 D7 to D0 Display memory RS MSB LSB H R12 D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are display memory data. D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are display memory data. R12 D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D1 are display memory data. D6 to D0 Index register RS MSB LSB L X 0 0 1 0 0 0 1 D7 to D0 Scroll step count register RS MSB LSB H 0 0 0 0 0 0 1 0 D6 to D0 Index register RS MSB LSB L X 0 0 0 0 1 1 0 D6 to D0 X address register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 depend on application condition. D6 to D0 Index register RS MSB LSB L X X 0 0 0 1 1 1 H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D1 depend on application condition. D6 to D0 Index register RS MSB LSB L X 0 0 0 1 1 0 0 Data Sheet S15649EJ2V0DS 57 PD161622 Display data Re-write scrolling area 1 (start) Display data Re-write scrolling area 2 Display data Re-write scrolling area n (end) Next transaction R12 D7 to D0 Display memory RS MSB LSB R12 D7 to D0 Display memory RS MSB LSB H R12 D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are display memory data. D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are display memory data. H (repeat) D7 D6 D5 D4 D3 D2 D1 D0 Caution D7 to D0 are display memory data. Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not meant for use in mass-production design. 58 Data Sheet S15649EJ2V0DS PD161622 (4) Scroll function example Scroll area start line register (R15): 2CH Scroll area line count register (R16): 58H (a) Scroll step count register setting (R17): 00H Source Gate 1 1 Fixed display area 44 45 2BH 2CH 132 Y address 00H Scroll area 132 133 Fixed display area 176 83H 84H AFH (b) Scroll step count register setting (R17): 01H Source Gate 1 1 Fixed display area 44 45 2BH 2DH 132 Y address 00H Scroll area 132 133 Fixed display area 176 83H 2CH 84H AFH Data Sheet S15649EJ2V0DS 59 PD161622 (c) Scroll step count register setting (R17): 02H Source Gate 1 1 Fixed display area 44 45 2BH 2EH 132 Y address 00H Scroll area 132 133 Fixed display area 176 83H 2CH 2DH 84H AFH (d) Scroll step count register setting (R17): 57H Source Gate 1 1 Fixed display area 44 45 2BH 83H 2CH 132 Y address 00H Scroll area 132 133 Fixed display area 176 82H 84H AFH 60 Data Sheet S15649EJ2V0DS PD161622 5.12 Stand-by The PD161622 has a stand-by function. Input of a stand-by command is acknowledged when the STBY bit of the control register 1 (R0) is set to 1. When the stand-by command has been input, the PD161622 is forcibly placed in the VSS display status, and scans the frame being display to the end. When scanning is complete, all gate outputs are turned on, the charge of the pixel on the TFT panel is decreased to 0, and the output stage amplifier and internal oscillator are stopped. The stand-by function is valid for only the source driver IC; the gate IC ( PD161640) and power IC ( PD161660) connected to the PD161622 are not controlled by this function. After executing the stand-by command, therefore, execute commands that turn off the regulator for the gate IC and power IC an turn off the DC/DC converter. When the stand-by status is released, turn on the DC/DC converter and the regulator of the gate IC and power IC, and then issue an ordinary operation command (STBY = 0), in the reverse order to which the stand-by command was input. Data Sheet S15649EJ2V0DS 61 PD161622 (1) Stand-by sequence Operating status (normal display) IR Control register 1 assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H X X D5 D8 D0 X 0 X 0 X 0 X 0 X 0 R0 Control register 1 setting D8 D0 X 0 X 0 X 1 X 0 X 0 Wait time 1 (tOE2RG) D7: Don't care D6: Don't care D4: Normal display mode (not partial display mode) D3: Stand-by ON D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. The source output is automatically fixed to the VSS level by standby, so D7 and D6 can be set to any value. At least one frame period D5 to D0 Index register D15 RS D7 X X X L X 0 0 X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 Note D8 D0 1 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator ON D0: DC/DC converter ON Note This setting can be deleted from the sequence when using an IC with no regulator circuit for the gate driver. Although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the LCD module. Wait time 2 (tRGRP) 62 Data Sheet S15649EJ2V0DS PD161622 IR Power supply control register 1 assignment RS D5 to D0 Index register D15 D7 X X X L X 0 0 X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter ON Although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the LCD module. IR D5 to D0 Index register D15 D7 X X X L X 0 0 Wait time 3 (tRGRP) Power supply control register 1 assignment RS X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 0 Stand-by setting completed D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter OFF Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not meant for use in mass-production design. Data Sheet S15649EJ2V0DS 63 PD161622 (2) Stand-by release sequence Stand-by status IR Control register 1 assignment RS D6 to D0 Index register D15 D7 X X X L X 0 0 X 0 X 0 X 0 X 0 D8 D0 X 0 R0 Control register 1 setting D7 to D0 Control register 1 D15 RS D7 X X X H 1 0 D5 D8 D0 X 0 X 0 X 0 X 0 X 0 D7: All data "1" output (normally white: white output) D6: Normal display D4: Normal display mode (not partial display mode) D3: Normal mode (stand-by release) D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. IR D5 to D0 Index register D15 D7 X X X L X 0 0 RS Power supply control register 1 assignment X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter ON tDDRP is the output stable period of the DC/DC converter. Although a setting of about 50 mS is the target, be sure to finalize the timing after sufficient evaluation with the LCD module. IR D5 to D0 Index register D15 RS D7 X X X L X 0 0 Wait time 1 (tDDRP) Power supply control register 1 assignment X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 1 D8 D0 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator ON D0: DC/DC converter ON 64 Data Sheet S15649EJ2V0DS PD161622 Wait time 2 (tRPRG) IR Power supply control register 1 assignment D5 to D0 Index register D15 RS D7 X X X L X 0 0 D8 D0 X 1 tRPRG is the output stable period of the DC/DC converter. Although a setting of about 20 mS is the target, be sure to finalize the timing after sufficient evaluation with the LCD module. X 1 X 1 X 0 X 0 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 1 Note D8 D0 1 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator ON D1: Power supply IC regulator ON D0: DC/DC converter ON Note This setting can be deleted from the sequence when using an IC with no regulator circuit for the gate driver. Input DISP ON command after all power supply is set up. Although a setting of about 1 mS is the target in tRPRG, be sure to finalize the timing after sufficient evaluation with the LCD module. Wait time 3 (tRGOE1) D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H 0 0 D5 X 0 X 0 X 0 X 0 D8 D0 X 0 R0 Control register 1 setting D8 D0 X 0 X 0 X 0 X 0 X 0 D7: Normal display (all data "1" output display ON) D6: Normal display D4: Normal display mode (not partial display mode) D3: Normal mode (stand-by release) D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. Next transaction Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not meant for use in mass-production design. Data Sheet S15649EJ2V0DS 65 PD161622 5.13 8-Color Dispaly Mode The PD161622 contains an 8-color display function for low-power-consumption driving. The mode can be switched to 8-color display mode by setting COLOR in control register 1 (R0) to 1. As shown in the figure below, in 8-color display mode, the PD161622 controls ON/OFF of each dot using the MSB of each dot data in the display RAM. It is therefore necessary to overwrite the display RAM data in accordance with the screen of each mode when changing from 65,000-color display mode to 8-color mode, and vice versa. In 8-color display mode, each source output is connected by switching the top and bottom grayscale voltages to enable direct driving of the TFT panel, which results in low power consumption. Figure 5-30. D15 Valid D14 Invalid D13 Invalid D12 Invalid D11 Invalid D10 Valid D9 Invalid D8 Invalid D7 Invalid D6 Invalid D5 Invalid D4 Valid D3 Invalid D2 Invalid D1 Invalid D0 Invalid Dot 1 Dot 2 1 pixel (= 1 x address) Dot 3 66 Data Sheet S15649EJ2V0DS PD161622 (1) 8-color display mode setting sequence example Previous statement (65.000-color display mode) IR Control register 1 assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H 0 1 D5 D8 D0 X 0 X 0 X 0 X 0 X 0 R0 Control register 1 assignment D8 D0 X 0 X 0 X 0 X 0 X 0 D7: Normal display D6: All data "0" output (normally white: black output) D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. In 8-color display mode, the value of the MSB of each dot data in the internal display RAM is used as the color data, making it necessary to overwrite the display RAM data when changing from 65,000-color display mode to 8-color display mode. IR D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 X address register D15 RS D7 X X X H 0 0 0 X address: 00H IR D6 to D0 Index register D15 RS D7 L X X X 0 X 0 X 0 X 0 X 1 X 1 X address register assignment X 0 X 0 X 1 X 1 D8 D0 X 0 R6 X address register setting D8 D0 X 0 X 0 X 0 X 0 X 0 Y address register assignment D8 D0 X 1 R7 Y address register setting D7 to D0 Y address register D15 RS D7 H X 0 X 0 X 0 X 0 X 0 X 0 X 0 D8 D0 X 0 Y address: 00H Data Sheet S15649EJ2V0DS 67 PD161622 IR Display memory register assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D8 D0 X 0 X 0 X 1 X 1 X 0 R12 Display data write 1 (start) D15 to D0 Display memory register D15 D8 RS D7 D0 D15 D10 X X X X X X H D4 X X X X X X X Caution D15, D10, and D4 are display memory data. When in 8-color mode, only D15, D10, and D4 data are valid. 0: OFF, 1: ON, (normally white) D15 to D0 Display memory register D15 D8 RS D7 D0 D15 D10 X X X X X X H D4 X X X X X X X Caution D15, D10, and D4 are display memory data. When in 8-color mode, only D15, D10, and D4 data are valid. 0: OFF, 1: ON, (normally white) D15 to D0 Display memory register D15 D8 RS D7 D0 D15 D10 X X X X X X H D4 X X X X X X X Caution D15, D10, and D4 are display memory data. When in 8-color mode, only D15, D10, and D4 data are valid. 0: OFF, 1: ON, (normally white) D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H 0 0 D5 R12 Display data write 2 R12 Display data write n (end) IR Control register 1 assignment X 0 X 0 X 0 X 0 D8 D0 X 0 R0 Control register 1 setting D8 D0 X 0 X 0 X 0 X 1 X D1 D7: Normal display D6: Normal display (display ON [All data "0" display normal mode]) D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 8-color display mode D1: Power mode is set in accordance with the usage conditions. D5 is set in accordance with the usage conditions. Next transaction Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not meant for use in mass-production design. 68 Data Sheet S15649EJ2V0DS PD161622 (2) Returning to 65,000-color display mode sequence Previous statement (8-color display mode) IR Control register 1 assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D8 D0 X 0 X 0 X 0 X 0 X 0 R0 Control register 1 setting D7 to D0 Control register 1 D15 D8 RS D7 D0 X X X X X X X X H 0 0 1 D1 0 0 0 D5 D7: Normal display D6: All data "0" output (normally white: black output) D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 8-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. In 8-color display mode, the value of the MSB of each dot date in the internal display RAM is used as the color data, making it necessary to overwrite the display RAM data when returning to 65,000-color display mode from 8-color display mode. IR X address register assignment RS D6 to D0 Index register D15 D7 X X X L X 0 0 X 0 X 0 X 1 X 1 D8 D0 X 0 R6 X address register setting D7 to D0 X address register D15 RS D7 X X X H 0 0 0 X address: 00H D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Y address register D15 RS D7 X X X H 0 0 0 Y address: 00H D8 D0 X 0 X 0 X 0 X 0 X 0 IR Y address register assignment X 0 X 0 X 1 X 1 D8 D0 X 1 R7 Y address register setting D8 D0 X 0 X 0 X 0 X 0 X 0 Data Sheet S15649EJ2V0DS 69 PD161622 IR Display memory register assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D8 D0 X 0 X 0 X 1 X 1 X 0 R12 Display data write 1 (start) D15 to D0 Display memory register D15 RS D7 D15 D14 D13 D12 D11 D10 H D7 D6 D5 D4 D3 D2 Caution D15 to D0 are display memory data. D15 to D0 Display memory register D15 RS D7 D15 D14 D13 D12 D11 D10 H D6 D5 D4 D3 D2 D7 Caution D15 to D0 are display memory data. D15 to D0 Display memory register D15 RS D7 D15 D14 D13 D12 D11 D10 H D7 D6 D5 D4 D3 D2 Caution D15 to D0 are display memory data. D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H 0 0 D5 D8 D0 D8 D0 D9 D1 R12 Display data write 2 D9 D1 D8 D0 D8 D0 R12 Display data write n (end) D8 D0 D8 D0 D9 D1 IR Control register 1 assignment D8 D0 X 0 X 0 X 0 X 0 X 0 R0 Control register 1 setting D8 D0 X 0 X 0 X 0 X 0 X 0 D7: Normal display D6: Normal display (display ON [All data "0" display normal mode]) D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. Next transaction Caution This sequence is shown only for the purpose of illustrating the command sequence, and is not meant for use in mass-production design. 70 Data Sheet S15649EJ2V0DS PD161622 5.14 Power ON/OFF An example of the standard power ON/OFF sequence in a chipset for driving a TFT-LCD panel that uses PD61622 is shown below. Note that this sequence diffes depending on the chipset configuration and TFT-LCD panel used. (1) Power ON sequence Power ON Hard reset (/RESET = L) Hard reset release (/RESET =H) IR Reset register assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Reset register D15 RS D7 X X X H X X X D8 D0 X 1 X 0 X 0 X 0 X 1 R3 Reset register setting D8 D0 X 1 X X X X X X X X X 1 X 1 X 0 X 0 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 0 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter OFF IR D6 to D0 Index register D15 RS D7 X X X L X 0 0 Power supply control register 2 assignment X 1 X 1 X 0 X 1 D8 D0 X 0 R26 Power supply control register 2 setting D7 to D0 Power supply control register 2 D15 RS D7 H X X X X X X D1 D8 D0 D0 D1 and D0 are set in accordance with the usage conditions. Data Sheet S15649EJ2V0DS 71 PD161622 IR Power supply control register 1 assignment RS D6 to D0 Index register D15 D7 X X X L X 0 0 X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 X X X X X H D5 D4 D3 X D6 D8 D0 X 1 X 1 X 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator ON D1: Power supply IC regulator ON D0: DC/DC converter ON IR D6 to D0 Index register D15 D7 X X X L X 0 0 VCOM output center value setting register assignment RS X 1 X 1 X 1 X 0 D8 D0 X 1 R29 VCOM output center value setting register setting D7 to D0 Power supply control register 1 D15 RS D7 X X X X X H D5 D4 D3 X D6 D8 D0 X 1 X 1 X 1 IR Output stage capacity setting register assignment D7 to D3 are set in accordance with the usage conditions. This register setting is not required when VCOMC (D3) of the output stage capacity setting register (R30) is 0. D6 to D0 Index register D15 RS D7 X X X L X 0 0 X 1 X 1 X 1 X 1 D8 D0 X 0 R30 Output stage capacity setting register setting D7 to D0 Power supply control register 1 D15 RS D7 X X X X X H D5 D4 0 0 D6 D8 D0 X D0 X D2 X D1 D7: g-correction circuit reference voltage generation amplifier drive/normal D3: VCOM amplifier operation (when in used) D6 to D4 are set in accordance with the usage conditions (capacity setting for COMMON center value setting amplifier (VCOM)). D2 to D0 are set in accordance with the usage conditions (source output capacity setting ). 72 Data Sheet S15649EJ2V0DS PD161622 IR Control register 1 assignment RS D6 to D0 Index register D15 D7 X X X L X 0 0 X 0 X 0 X 0 X 0 D8 D0 X 0 R0 Control register 1 setting D7 to D0 Control register 1 D15 RS D7 X X X H 1 0 D5 D8 D0 X 0 X 0 X 0 X 0 X 0 D7: All data "1" output (normally white: white output) D6: Normal display D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. IR D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 2 D15 RS D7 X X X H X X D5 Control register 2 assignment X 0 X 0 X 0 X 0 D8 D0 X 1 R1 Control register 2 setting D8 D0 X 0 X D4 X 0 X 0 X 0 D1: 1 line time = tcal (normal setting) D0: Line inversion driving D5 and D4 are set in accordance with the usage condtions. Caution Always write 0 to D3 and D2. IR D6 to D0 Index register D15 RS D7 L X X X 0 X 0 X 0 X 0 X 1 X 0 Data access control register assignment D8 D0 X 1 R5 Data access control register setting D7 to D0 Data access control register D15 RS D7 H X 0 X 0 X 0 X 0 X 0 X 0 X 0 D8 D0 X 0 D7: 16-bit data bus D6: Normal write mode D4: Normal operation (not window access mode) D2: Access to X address direction D1: X address increment D0: Y address increment Caution Always write 0 to D5 and D3. Data Sheet S15649EJ2V0DS 73 PD161622 IR Calibration register assignment RS D6 to D0 Index register D15 D7 X X X L X 0 1 X 0 X 1 X 1 X 0 D8 D0 X 1 R45 Calibration register setting (calibration start) D7 to D0 Calibration register D15 RS D7 X X X H X X X D8 D0 X 1 X X X X X X X X Calibration time IR Calibration register assignment D6 to D0 Index register D15 RS D7 X X X L X 0 1 D7 to D0 Calibration register D15 RS D7 X X X H X X X D8 D0 X 1 Calibration wait time (tcal) tcal = 1 / (frame frequency x177) X 0 X 1 X 1 X 0 R45 Calibration register setting (calibration stop) IR X address register assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 X address register D15 RS D7 X X X H 0 0 0 X address: 00H D6 D0 RS X X X X X X X X D8 D0 X 0 X 0 X 0 X 1 X 1 D8 D0 X 0 R6 X address register setting D8 D0 X 0 X 0 X 0 X 0 X 0 IR Y address register assignment L R7 Y address register setting D15 D7 X X X 0 X 0 X 0 X 0 X 1 X 1 D8 D0 X 1 D7 to D0 Y address register D15 RS D7 X X X H 0 0 0 Y address: 00H X 0 X 0 X 0 X 0 D8 D0 X 0 74 Data Sheet S15649EJ2V0DS PD161622 IR Display memory register assignment D6 to D0 Index register D15 RS D7 L R12 Display data write 1 (start) D15 to D0 Display memory register D15 RS D7 H R12 Display data write 2 D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D8 D0 D8 D0 X X X 0 X 0 X 0 X 1 X 1 X 0 D8 D0 X 0 Caution D15 to D0 are display memory data. D15 to D0 Display memory register D15 RS D7 H D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D8 D0 D8 D0 Caution D15 to D0 are display memory data. R12 Display data write n (end) D15 to D0 Display memory register D15 RS D7 H IR Control register 1 assignment D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D8 D0 D8 D0 Caution D15 to D0 are display memory data. RS D6 to D0 Index register D15 D7 L X 0 0 0 0 0 0 D8 D0 0 R0 Control register 1 setting D7 to D0 Control register 1 D15 RS D7 X X X H 0 0 D5 D8 D0 X 0 X 0 X 0 X 0 X 0 D7: Normal display(display ON [All data "0" display normal mode]) D6: Normal display D4: Normal display mode (not partial display mode) D3: Stand-by OFF D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. Next transaction Caution This sequence is shown only for the purpose of illustrating the sequence from power application to display ON, and is not meant for use in mass production design. Note also that this sequence differs depending on the configuration of the chipset and TFT-LCD module Data Sheet S15649EJ2V0DS 75 PD161622 (2) Power OFF sequence Operating status (normal display) IR Control register 1 assignment D6 to D0 Index register D15 RS D7 X X X L X 0 0 D7 to D0 Control register 1 D15 RS D7 X X X H X X D5 D8 D0 X 0 X 0 X 0 X 0 X 0 R0 Control register 1 setting D8 D0 X 0 X 0 X 1 X 0 X 0 D7: Don't care D6: Don't care D4: Normal display mode (not partial display mode) D3: Stand-by ON D2: 65,000-color display mode D1: Normal power mode D5 is set in accordance with the usage conditions. The source output is automatically fixed to the VSS level by standby, so D7 and D6 can be set to any value. At least one frame period Wait time 1 (tOE2RG) D5 to D0 Index register D15 RS D7 X X X L X 0 0 X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 Note D8 D0 1 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator ON D0: DC/DC converter ON Note This setting can be deleted from the sequence when using an IC with no regulator circuit for the gate driver. Although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the LCD module. Wait time 2 (tRGRP) 76 Data Sheet S15649EJ2V0DS PD161622 IR Power supply control register 1 assignment RS D5 to D0 Index register D15 D7 X X X L X 0 0 X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 1 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter ON Although a setting of 0 ns has no negative effect in terms of the device, be sure to finalize the timing after sufficient evaluation with the LCD module. IR D5 to D0 Index register D15 D7 X X X L X 0 0 Wait time 3 (tRGRP) Power supply control register 1 assignment RS X 1 X 1 X 0 X 0 D8 D0 X 1 R25 Power supply control register 1 setting D7 to D0 Power supply control register 1 D15 RS D7 H X D6 D5 D4 D3 0 0 D8 D0 0 D6 to D3 are set in accordance with the usage conditions. D2: Gate driver regulator OFF D1: Power supply IC regulator OFF D0: DC/DC converter OFF Do not need to input RESET in source driver, however, when power off, system reset is set up to /RESET = L by timing DCON (R25: D0). Hard reset (/RESET = L) Power OFF Caution This sequence is shown only for the purpose of illustrating the sequence up to when the power is turned off, and is not meant for use in mass-prodution design. Note also that this sequence differs depending on the configuration of the chipset and TFT-LCD module. Data Sheet S15649EJ2V0DS 77 PD161622 6. RESET If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset command will also initialize each register to its default value. These default values are listed in the table below. Register Index register Control register 1 Control register 2 Data access control register X address register Y address register MIN. X address register MAX. X address register MIN. Y address register MIN. Y address register Display memory register Note2 Rn IR R0 R1 R5 R6 R7 R8 R9 R10 R11 R12 R15 R16 R17 R19 R20 R21 R22 R23 R25 R26 R29 R30 R31 R36 R37 R38 R39 R40 R42 R45 R46 R49 R50 R114 R115 /RESET Pin X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Note1 Reset Command O O O O O O O O O O X O O O O O O O O O O O O O O O O O O O O O O O O O O Default Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H - 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 06H 00H 00H 00H 00H 00H Scroll area start line register Scroll area line count register Scroll step count register Partial off area color register Partial 1 display area start line register Partial 2 display area start line register Partial 1 display area line count register Partial 2 display area line count register Power supply control register 1 Power supply control register 2 VCOM output center value setting register Output stage capacity setting register -reference-voltage generator capacity setting register -contrast value setting register 1 -contrast value setting register 2 -contrast value setting register 3 -contrast value setting register 4 Pre-charge direction setting data register -correction input disconnect register Calibration register Output port register Input port register Interface operating voltage setting register Internal logic operating voltage setting register Test mode Note 3 Pre-charge period supplement pulse setting register Remark O: Default value set, X: Default value not set Notes 1. The internal counters are initialized only by a reset from the /RESET pin. Be sure to perform reset via the /RESET pin at power application. 2. The contents of RAM are saved in the case of both reset by /RESET pin and reset by reset command. Note that the RAM contents are undifined. immediately after the power is turned on. 3. The following value is set as the calibration setting time, tcal, in a reset by reset command. tcal = 1/fOSC x 37 78 Data Sheet S15649EJ2V0DS PD161622 7. COMMAND The PD161622 identifies data bus signals by a combination of the RS, /RD (E), and /WR (R,/W) signals. It interprets and executes commands only in accordance with the internal timing, without being dependent upon the external clock. Therefore, the processing speed is extremely high and, usually, no busy check is necessary. An i80 system CPU interface inputs a low pulse to the /RD pin when it reads data to issue a command. It inputs a low pulse to the /WR pin when it writes data. Data can be read from an M68 system CPU interface if a high-pulse signal is input to the R,/W pin, and written if a low-pulse signal is input to the R,/W pin. A command is executed if a high-pulse signal is input to the E pin in this status. Therefore, in the explanation of the commands and display commands after 7.2 Control Register 1 (R0) and the sections that follow, the M68 system CPU interface uses H, instead of /RD (E), when reading status or display data. This is how it differs from the i80 system CPU interface. The commands of the PD161622 are explained below, taking an i80 system CPU interface as an example. When the serial interface is used, sequentially input data to the PD161622, starting from D7. The data bus length to input commands is as follows: * Commands other than those that manipulate the display memory register (R12) are input in one byte unit, regardless of the value of BMD (control register 2 (R1), bus length setting). * The commands that manipulate the display memory register (R12) are input in 1-byte units when BMD = 1, or in 2-byte units when BMD = 0. (1) Commands other than those that manipulate display memory register (R12) BMD = 1 (8-bit data bus) Pin DATA D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 BMD = 0 (16-bit data bus) Pin DATA D15 Note D14 Note D13 Note D12 Note D11 Note D10 Note D9 Note D8 Note D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Note 0 or 1 (2) Display Memory Register (R12) BMD = 1 (8-bit data bus) Pin DATA D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 BMD = 0 (16-bit data bus) Pin DATA D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Data Sheet S15649EJ2V0DS 79 PD161622 7.1 Command List Index Register 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 CS RS Rn Register Name Index register Control register 1 Control register 2 Reset register Data access control register X address register Y address register MIN. .X address register MAX. . X address register MIN. .Y address register MAX. . address register Y Display memory register R/W Data Bits 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 IR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 IR0 IR4 IR3 IR2 IR7 IR6 IR1 IR5 W R/W DISP1 DISP0 ADC DTY STBY COLOR LPM GSM R/W VSEL GSEL LTS INV W R/W R/W R/W R/W R/W R/W R/W W BMD BSTR XA7 XA6 XA5 YA7 YA6 YA5 WAS XA4 XA3 YA4 YA3 CRES INC XDIR YDIR XA2 XA1 XA0 YA2 YA1 YA0 XMIN7 XMIN6 XMIN5 XMIN4 XMIN3 XMIN2 XMIN1 XMIN0 XMAX7 XMAX6 XMAX5 XMAX4 XMAX3 XMAX2 XMAX1 XMAX0 YMIN7 YMIN6 YMIN5 YMIN4 YMIN3 YMIN2 YMIN1 YMIN0 YMAX7 YMAX6 YMAX5 YMAX4 YMAX3 YMAX2 YMAX1 YMAX0 D7 D6 D5 D4 D3 D2 D1 D0 Scroll area start line register Scroll area line count register Scroll step count register Partial off area color register Partial 1 display area start line register Partial 2 display area start line register Partial 1 display area line count register Partial 2 display area line count register Power supply control register 1 Power supply control register 2 R/W SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 R/W SAW7 SAW6 SAW5 SAW4 SAW3 SAW2 SAW1 SAW0 R/W SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0 R/W R/W R/W R/W R/W R/W R/W PGR P1SL7 PGG PGB P1SL6 P1SL5 P1SL4 P1SL3 P1SL2 P1SL1 P1SL0 P2SL7 P2SL6 P2SL5 P2SL4 P2SL3 P2SL2 P2SL1 P2SL0 P1AW7 P1AW6 P1AW5 P1AW4 P1AW3 P1AW2 P1AW1 P1AW0 P2AW7 P2AW6 P2AW5 P2AW4 P2AW3 P2AW2 P2AW1 P2AW0 BGRS VCE VCD2 PVCOM RGONG RGONP DCON VCD12 VCD11 VCOM output center value setting register Output stage capacity setting register -reference-voltage generator setting register R/W EV7 R/W BPL R/W WHP EV6 CI2 WI2 EV5 CI1 WI1 EV4 CI0 WI0 EV3 VCOMC BHP EV2 SF2 BI2 EV1 SF1 BI1 EV0 SF0 BI0 -contrast value setting register 1 -contrast value setting register 2 -contrast value setting register 3 -contrast value setting register 4 Pre-charge direction setting data register -correction input disconnect register R/W R/W R/W R/W R/W R/W GPH7 GNH7 GPL7 GNL7 GPH6 GNH6 GPL6 GNL6 GPH5 GNH5 GPL5 GNL5 GPH4 GNH4 GPL4 GNL4 GPH3 GNH3 GPL3 GNL3 GPH2 GNH2 GPL2 GNL2 GPH1 GNH1 GPL1 GNL1 GPH0 GNH0 GPL0 GNL0 RDTP3 RDTP2 RDTP1 RDTP0 RDTN3 RDTN2 RDTN1 RDTN0 GHSW Calibration register Pre-charge period supplement pulse setting register R/W R/W OC PLIM6 PLIM5 PLIM4 PLIM3 PLIM2 PLIM1 PLIM0 Output port register Input port register R/W R OP7 OP6 OP5 OP4 OP3 IP3 OP2 IP2 OP1 IP1 OP0 IP0 R114 Interface operating voltage setting register R115 Internal logic operating voltage setting register R/W R/W RTSC1 RTSC0 RTSL1 RTSL0 Remark : These registers cannot be used. Cautions 1. If a write-only register is read, invalid data will be output. 2. A low level is output when an unused register is read. 80 Data Sheet S15649EJ2V0DS PD161622 7.2 Command Explanation (1/9) Resistor R0 Bit D7 Symbol DISP1 Function This command performs the same output as when all data is 1, independently of the internal RAM data (white display in the case of normally white). This command is executed, after it has been transferred, when the next line is output. 0: Normal operation 1: Ignores data of RAM and outputs all data as 1. DISP1 takes precedence over DISP0. When DISP1 = H, DISP0 = H is ignored. D6 DISP0 This command performs the same output as when all data is 0, independently of the internal RAM data (black display in the case of normally white). This command is executed, after it has been transferred, when the next line is output. 0: Normal operation 1: Ignores data of RAM and outputs all data as 0. D5 ADC Column address direction This command can be used to select the direction of source driver output. For more detail, refer to 5.2.3 Column address circuit D4 DTY This pin selects the partial function. When partial display mode is selected, partial off area color is displayed by setting partial off area color register (R19). The power consumption cannot be reduced with the partial function. To reduce the power consumption, select the 8-color mode. This command is executed following transfer from the time the next line data is output. 0: Normal display mode 1: Partial display mode D3 STBY This bit selects the stand-by function. When the stand-by function is selected, a display OFF operation is executed and the amplifiers at each output stage and the operation of internal oscillation circuit are stopped. However, stand-by control cannot be performed for the gate IC ( PD161640) connected to PD161622 and the power-supply IC ( PD161660). Therefore, after executing the stand-by function using this bit, set both the regulator for the gate IC and power-supply IC to off and set the DC/DC converter to OFF. For the sequence, refer to the preliminary product information machine of the PD161660. Note that when releasing stand-by, perform the opposite operation, i.e., after setting the DC/DC converter to ON and setting the regulators of the gate IC and power-supply IC to ON, execute the normal operation command. 0: Normal operation 1: Stand-by function (display read off from RAM, stop both OSC and VCOM, display OFF = entire data is output as 1) D2 COLOR This pin switches the 65,000-color mode and the 8-color mode. When the 8-color mode is selected, low power supply can be selected in order to stop the amplifier at each output stage. In the 8-color mode, the value of the MSB of the internal RAM data is used as the color data. This command is executed following transfer from the time the next line data is output. 0: 65,000-color mode (16 bits/pixels) 1: 8-color mode (3 bits/pixels) Data Sheet S15649EJ2V0DS 81 PD161622 (2/9) Resistor R0 D1 Bit Symbol LPM Function This bit is used when setting the gate IC ( PD161640) and power-supply IC ( PD161660) to the low-power mode. When the low-power mode is selected, the LPMG pin and the LPMP pin signals change from low to high (output changes immediately following command execution.). The LPMG pin must be connected to the LPM pin of the gate IC, and the LPMP pin must be connected to the LPM pin of the power-supply IC. 0: Normal 1: Low power mode D0 GSM Sets output of the gate scanning signal during partial display. When 1 is selected, gate scanning of the line set in the partial non-display area is stopped. 0: Normal mode 1: Stops gate scanning in partial non-display area R1 D5 VSEL Sets the potential of the pre-charge output of the LCD driver. The maximum/minimum output potential of the pre-charge output is: 0: Power supply voltage (outputs VS and VSS) 1: Maximum output level of internal -output adjustment circuit (uses VPH, VNH, VPL, VNL) IF VSEL = 0, VS or VSS is automatically output as the pre-charge output. D4 GSEL Sets the maximum/minimum output voltage of the -correction resistor. If the internal -output adjustment circuit is selected, the maximum/minimum output potential of the -correction resistor is: 0: Supply voltage (outputs VS and VSS). 1: Voltage of internal -output adjustment circuit (uses VPH, VNH, VPL, VNL) 8-color mode (3 bits/pixels) D1 LTS Selects set time of calibration. The calibration function adjusts the frame frequency by setting time of one line. This command can select the set time of a line from the following: 0: 1 line time = tcal 1: 1 line time = tcal x 2 (tcal: Calibration set time1 = 1 / Frame frequency / Number of displayed lines) D0 INV This bit selects between the line inversion function and the frame inversion function. The mode selected by this command is executed from the start of the next scan after the gate scan in progress when this command was executed has completed 176 lines. When the reset command is input, the INV register is initialized. 0: Line inversion with same line. 0: Line inversion 1: Frame inversion R3 D0 CRES Command reset function. Be sure to execute this bit after power ON. Command reset automatically clears this bit following execution (CRES = 01H). Therefore, it is not necessary to set 0 (select normal operation) again by software. Moreover, since the time required for the value of this bit to change (1 0) following command reset execution is extremely short, it is not necessary to secure time until the next command is set following command reset setting. 0: Normal operation 1: Command reset 82 Data Sheet S15649EJ2V0DS PD161622 (3/9) Resistor R5 D7 Bit Symbol BMD 0: 16-bit data bus 1: 8-bit data bus This command is invalid when the serial interface is used. D6 BSTR Sets the write mode for writing data to the display RAM. If the high-speed RAM write mode is selected, data is written to the display RAM in 64-bit units inside the PD161622. When selecting the high-speed RAM write mode, be sure to write data to the display RAM in 64-bit units. 0: Normal write mode (16-bit access) 1: High-speed RAM write mode (64-bit access) D4 WAS Window access mode setting When the window access mode is set, the address is incremented/decremented only in the range set by the MIN. X address setting register (R8), MAX. X address setting register (R9), MIN. Function Sets the bus width when the parallel interface is used. Y address setting register (R10), and MAX. Y address setting register (R11). 0: Normal operation 1: Window access mode D2 INC Selects the direction in which the display RAM address is to be incremented/decremented. Whether the X address and Y address are incremented or decremented is specified by XDIR (R5: D1) and YDIR (R5: D0), respectively. 0: Access in X address direction 1: Access in Y address direction D1 XDIR Specifies whether the display RAM address is incremented or decremented in the X address direction. 0: Increments X address 1: Decrements X address D0 YDIR Specifies whether the display RAM address is incremented or decremented in the Y address direction. 0: X address increment 1: X address decrement R6 R7 R8 D7 to D0 D7 to D0 D7 to D0 XAn YAn XMINn This register sets the X address of the display RAM. Set a value between 00H and 83H. This register sets the Y address of the display RAM. Set a value between 00H and AFH. Sets the minimum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MAX. Set a value between 00H to 82H. R9 D7 to D0 XMAXn Sets the maximum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MIN. Set a value between 01H to 83H. R10 D7 to D0 YMINn Sets the minimum value of the T address in the window access mode. The Y address is incremented up to the maximum value set by the MAX. (R11), and then initialized to the address value set by this command. (R5: YDIR = 0) Set a value between 00H to AEH. X address register (R9), and then initialized to the address value set by this command. (R5: XDIR = 0) X address register (R8), and then initialized to the address value set by this command. (R5: XDIR = 0) Y address register Data Sheet S15649EJ2V0DS 83 PD161622 (4/9) Resistor R11 Bit D7 to D0 Symbol YMAXn Function Sets the maximum value of the Y address in the window access mode. The Y address is incremented up to the address value set by this command, and then initialized to the minimum address value set by the MIN. Y address register (R10) (R5: YDIR = 0) Set a value between 01H to AFH. R12 R15 D7 to D0 D7 to D0 Dn SSLn These bits are used for reading/writing data from/to display memory (internal RAM). Scroll area start line register (00H to AFH) When the screen is scrolled, the screen of the number of lines set by the scroll area line count register (R16) is scrolled up by the number of steps set by the scroll step count register (R17), starting from the line set by this command. R16 D7 to D0 SAWn Scroll area line count register (00H to AFH) When the screen is scrolled, the screen of the number of lines set by this command is scrolled up by the number of steps set by the scroll step count register (R17), starting from the line set by the scroll area start line register (R15) R17 D7 to D0 SSTn Scroll step count register (00H to AFH) When the screen is scrolled, the screen of the number of lines set by the scroll area line count register (R16) and the scroll step count register (R17) is scrolled up by the number of steps set by this command. Note that because this command is invalid in the partial display mode, the scroll function cannot be used. R19 D2 PGR Partial off area color register Sets the color of the screen other than the partial display area during partial display (R0: DTY = 1). One of eight colors can be selected (RGB: 1 bit each) as the off color. D1 PGG The relationship between each color data and the bits of this register is as follows. This relationship is not dependent upon the value of ADC. D0 PGB PGR: R OFF= 0, ON = 1 PGG: G OFF= 0, ON = 1 PGB: B OFF= 0, ON = 1 R20 D7 to D0 P1SLn Partial 1 display area start line register (00H to AFH) During partial display (R0: DTY = 1), the area starting from the line set by this command and ending as set by the partial 1 display area line count register (R22) is the partial 1 display area. R21 D7 to D0 P2SLn Partial 2 display area start line register (00H to AFH) During partial display (R0: DTY = 1), the area starting from the line set by this command and ending as set by the partial 2 display area line count register (R23) is the partial 2 display area. R22 D7 to D0 P1AWn Partial 1 display area line count register (00H to AFH) An area starting from the line set by the partial 1 display area start register (R20) and ending as set by this command is the partial 1 display area. If this register is 0, the values of the partial 2 display area start line register (R29) and the partial 2 display area line count register (R31) are not valid. R23 D7 to D0 P2AWn Partial 2 display area line count register (00H to AFH) An area starting from the line set by the partial 2 display area start register (R21) and ending as set by this command is the partial 2 display area. If the partial 1 display area line count register is 0, the values of the partial 2 display area start line register (R21) and partial 2 display area line count register (R23) are not valid. 84 Data Sheet S15649EJ2V0DS PD161622 (5/9) Resistor R25 Bit D6 Symbol BGRS Function This pin selects whether to use the internal power supply or an external power supply (input from the BRGIN pin) for generation the common center voltage output from the VCOM pin. 0: The internal power-supply is selected as the VCOM power supply 1: Input from the external power-supply BGRIN is selected as the VCOM power supply D5 VCE Selects the VO output level of the power-supply IC ( PD161660). The VCE pin of the PD161622 and the VCE pin of the power-supply IC must be connected. 0: The Vo high-level booster voltage level is VDD1 minus 1 level 1: The Vo high-level booster voltage level is the same level as VDD1 D4 VCD2 Selects the VDD2 output level of the power-supply IC ( PD161660). The VCD2 pin of the PD161622 and the VCD2 pin of the power-supply IC must be connected. 0: VDD2 = VDC x 2 1: VDD2 = VCD x 3 D3 PVCOM Sets the pre-charge time of a 1-line output period. 0: VBGR (3.0 V TYP.) 1: VS D2 RGONG Switches the internal regulator of the gate IC ( PD161640) ON/OFF. When OFF is selected, a low level is output from the RGONG pin, and when ON is selected, a high level is output from the RGONG pin. The RGONG pin of the PD161622 and the RGON pin of the gate IC must be connected. 0: Regulators of gate driver (VB) are OFF 1: Regulators of gate driver (VB) are ON D1 RGONP Switches the internal DC/DC converter of the power-supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the RGONP pin, and when ON is selected, a high level is output from the RGONP pin. The RGONP pin of the PD161622 and the RGON pin of the power-supply IC must be connected. 0: Regulators of power-supply IC (VT, VS) are OFF 1: Regulators of power-supply IC (VT, VS) are ON D0 DCON Switches the internal DC/DC converter of the power-supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the DCON pin, and when ON is selected, a high level is output from the DCON pin. The DCON pin of this IC and the DCON pin of the power-supply IC must be connected. 0: DC/DC converter is OFF 1: DC/DC converter is ON R26 D1 VCD12 Performs booster control for the DC/DC converter in the power-supply IC ( PD161660) The data set with this bit is output from the VCD11 pin and the VCD12 pin. The VCD11 pin and VCD12 pin of PD161622 must be connected to the VCD11 pin and the VCD12 D0 VCD11 pin of the power-supply IC. VCD12, VCD11 = 0, 0: VDD1 = VDC x 4 = 0, 1: VDD1 = VDC x 5 = 1, 0: VDD1 = VDC x 6 = 1, 1: VDD1 = VDC x 7 Data Sheet S15649EJ2V0DS 85 PD161622 (6/9) Resistor R29 Bit D7 to D0 Symbol EVn Function Sets the D/A converter circuit used to adjust the voltage of the reference voltage generator circuit (VBGR) input to the voltage regulator that sets the center value of the panel common drive output. The D/A converter divides the constant voltage generated by the reference voltage generator (VBGR) by 256, and one level can be selected between VBGR and VSS by setting this command. For more detail, refer to 5.5 Common Adjustment Circuit and 5.8 D/A Converter Circuit. R30 D7 BPL Switched the capacity of the -correction circuit reference voltage generation amplifiers on the side not being used (VPH, VPL, VNH, VNL) to the minimum value based on the polarity inversion timing in order to reduce the current consumption. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal 1: Reference voltage generation amplifier capacity switch drive D6 to D4 CIn Sets the bias current of the amplifier for setting the panel's COMMON drive waveform center value (VCOM), as shown in the table below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. CI2 0 0 0 0 1 1 1 1 CI1 0 0 1 1 0 0 1 1 CI0 0 1 0 1 0 1 0 1 VCOM Center Value Setting Amplifier Bias Current Value 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A D3 VCOMC Selects whether to use the amplifier for setting the panel's COMMON drive waveform center value (VCOM) or not. This amplifier can be used under conditions such as when an external COMMON drive circuit is being used. 0: VCOM amplifier operating 1: VCOM amplifier stopped D2 to D0 SFn Sets the capacity of the source output (S1 to S396), as shown in the table below. Determine the output capacity after sufficient evaluation with the actual TFT panel to be used. SF2 0 0 0 0 1 1 1 1 SF1 0 0 1 1 0 0 1 1 SF0 0 1 0 1 0 1 0 1 0.20 A 0.15 A 0.25 A 0.10 A 0.20 A 0.30 A 0.40 A 0.05 A Source Output Bias Current Value 86 Data Sheet S15649EJ2V0DS PD161622 (7/9) Register R31 D7 Bit Symbol WHP Function Sets the output mode of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal mode 1: High-power mode (output stage capacity: twice that of normal mode) D6 to D4 WIn Sets the output bias current of the reference voltage generator amplifier for setting the white level of the positive-polarity and negative-polarity sides (when VPL and VNL are normally white), as shown below. WI2 0 0 0 0 1 1 1 1 WI1 0 0 1 1 0 0 1 1 WI0 0 1 0 1 0 1 0 1 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A Amplifier Bias Current D3 BHP Sets the output mode of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. 0: Normal mode 1: High-power mode (output stage capacity: twice that of normal mode) D2 to D0 BIn Sets the output bias current of the reference voltage generator amplifier for setting the black level of the positive-polarity and negative-polarity sides (when VPH and VNH are normally white), as shown below. Determine the amplifier capacity after sufficient evaluation with the actual TFT panel to be used. BI2 0 0 0 0 1 1 1 1 BI1 0 0 1 1 0 0 1 1 BI0 0 1 0 1 0 1 0 1 0.20 A 0.50 A 0.10 A 0.05 A 1.00 A 1.50 A 2.00 A 3.00 A Amplifier Bias Current R36 R37 R38 R39 D7 to D0 D7 to D0 D7 to D0 D7 to D0 GPHn GNHn GPLn GNLn Sets the voltage value of the black level of positive polarity. For more det020ail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of negative polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of positive polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Sets the voltage value of the white level of positive polarity. For more detail, refer to 5.9 -Curve Correction Power Supply Circuit. Data Sheet S15649EJ2V0DS 87 PD161622 (8/9) Register R40 Bit D7 to D4 Symbol RDTPn Function Sets the data value at which the pre-charge direction is switched during positive-polarity drive. The value set to RDTPn corresponds to the higher 4bits of display RAM data DBn (6 bits for each of RFB), as shown below. RDTP3 Dot 1 (R) Dot 2 (G) Dot 3 (B) D15 D10 D4 RDTP2 D14 D9 D3 RDTP1 D13 D8 D2 RDTP0 D12 D7 D1 D3 to D0 RDTNn Sets the data value at which the pre-charge direction is switched during negative-polarity drive. The value set to RDTNn corresponds to the higher 4 bits of display RAM data DBn (6 bits for each of RGB), as shown below. RDTN3 Dot 1 (R) Dot 2 (G) Dot 3 (B) D15 D10 D4 RDTN2 D14 D9 D3 RDTN1 D13 D8 D2 RDTN0 D12 D7 D1 R42 D0 GHSW Controls the -correction voltage input pins (V0 to V5) and the switch for connecting the PD161622 internal -correction resistor. 0: Switch OFF (disconnected) 1: Switch ON (connected) R45 D0 OC This bit is used for calibration. The time from calibration start command execution until calibration stop command execution becomes the time for 1 line. 0: Calibration stop 1: Calibration start R46 D7 to D0 PLIMn Set the pre-charge time of a 1-line output period. The number of clocks set in this register + 2 CLK (1/fOSC) becomes the pre-charge time when one line is driven. For details, refer to 5.4.1 Drive timing R49 D7 to D0 OPn Output port (OP7 to OP0) write When after the output port register (R49) is specified in the index register, writing to the -correction input disconnect register (R42) is performed, the values written to the OP7 to OP0 pins are output. R50 D3 to D0 IPn Input port (IP3 to IP0) read To read the IP3 to IP0 inputs, use the following method. 88 Data Sheet S15649EJ2V0DS PD161622 (9/9) Register R114 Bit D1, D0 Symbol RTSCn Function Selects the optimum internal circuit operation based on the operating voltage of the interface circuits. The following settings are recommended based on this register. RTSC1 1 RTSC0 1 Caution Always set this register and internal logic operating voltage setting register (R115) to the same value. R115 D1, D0 RTSLn Selects the optimum internal circuit operation based on the operating voltage of the internal logic circuits. The following settings are recommended based on this register. RTSC1 1 RTSC0 1 Caution Always set this register and interface operating voltage setting register (R114) to the same value. Data Sheet S15649EJ2V0DS 89 PD161622 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, VSS = 0 V) Parameter Power supply voltage Power supply voltage Power supply voltage Power supply voltage for -curve correction Input voltage Input current Operating ambient temperature Storage temperature VS VCC1 VCC2 V1 to V5 VI II TA Tstg Symbol Ratings -0.5 to +6.5 -0.5 to +4.0 -0.5 to VCC1 + 0.5 -0.5 to VS + 0.5 -0.5 to VCC1 + 0.5 10 -40 to +85 -55 to +125 Unit V V V V V mA C C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V) Parameter Power supply voltage VS VCC1 VCC2 Input voltage VI1 VI2 Note1 Note2 Symbol MIN. 4.3 2.5 1.7 0 0 TYP. 5.0 2.7 1.8 MAX. 5.5 3.6 VCC1 VCC1 VCC2 Unit V V V V V Notes 1. Pins of VCC1 power-supply system: TOUT0 to TOUT15, IP0 to IP3, OP0 to OP7, LPMG, LPMP, GOE1, GOE2, GSTB, GCLK, DCON, RGONP, RGONG, VCD11, VCD12, VCD2, VCE, RSEL, TSTRTST, TSTVIHL, OSCIN 2. Pins of VCC2 power-supply system: /CS, /RD(E), /WR(R,/W), D0 to D5, D6(SCL), D7(SI), RS, /RESET, C86, PSX 90 Data Sheet S15649EJ2V0DS PD161622 Electrical Specifications (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 V to VCC1, VS = 4.3 to 5.5 V) Parameter Symbol VCC1 VCC2 VCC1 VCC2 VCC1, IOUT = -100 A VCC2, IOUT = -1 mA VCOUT1, VCOUT2, IOUT = -100 A VCC1, IOUT = 100 A VCC2, IOUT = 1 mA VCOUT1, VCOUT2, IOUT = 100 A ISOURCE = 100 A ISINK = -100 A Except D0 to D15 Except D0 to D15 D0 to D15 D0 to D15 VX = 3.5 V, VOUT = 4.5 V, VS = 5.0 V IVOL VCOM ICC1 ICC2 ISTBY IS VCC1 (when non-access CPU) VCC2 (when non-access CPU) VCC1 (stand-by mode) VS (65,000-color mode) VS (8-color mode) Driver output Current (pre-charge) Output voltage deviation IVOH IVOL VO1 VO2 Note3 Note2 Note2 Note3 Note2 Condition MIN. Specification TYP. Note1 Unit MAX. V V 0.2 VCC1 0.2 VCC2 V V V V V 0.1 VCC1 0.2 VCC2 0.1 VS V V V mV VCOM + 0.3 1 -1 10 -10 mV High level input voltage VIH1 VIH2 0.8 VCC1 0.8 VCC2 Low level input voltage VIL1 VIL2 High level output voltage VOH1 VOH2 VOH3 0.9 VCC1 0.8 VCC2 0.9 VS Low level output voltage VOL1 VOL2 VOL3 VCOM output voltage VCOMH VCOML VCOM - 0.3 High level input current Low level input current High level leakage current Low level leakage current High level driver output current Low level driver output current VCOM common output voltage fluctuation parameter Current consumption IIH1 IIL1 ILIH ILIL IVOH A A A A A -85 30 -10 140 0.2 1 600 45 -0.14 0.1 -20 -30 0.25 20 30 10 240 5 10 1000 100 -0.07 VX = 1.5 V, VOUT = 0.5 V, VS = 5.0 V Note2 A % A A A A A mA mA mV mV VS = 5.0 V, VOUT = VS - 0.1 V VS = 5.0 V, VOUT = VS + 0.1 V VOUT = 1.3 V to (VS - 1.3 V) VOUT = 0.3 to 1.3 V Note2 Note2 , (VS - 1.3 V) to (VS - 0.3 V) Notes 1. TYP. values are reference values when TA = 25C 2. VX refers to the output voltage of analog output pins S1 to S396. VOUT refers to the voltage applied to analog output pins S1 to S396 3. Frame frequency, line inversion mode selection, dot checkerboard input pattern, no load Data Sheet S15649EJ2V0DS 91 PD161622 Switching characteristics (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 V to VCC1, VS = 5.0 V) Pre-charge period tPLH1 Driver output period tPHL2 VO MAX. -200 mV Goal voltage +200 mV Goal voltage -200 mV tPLH2 VOUT VO MIN. +200 mV tPHL1 Parameter Driver output delay time 1 (pre-charge period) Driver output delay time 2 (driver output period) Symbol tPLH1 tPHL1 tPLH2 tPHL2 VS = 5.0 V, 4 k +27 pF Condition VO MAX. -200 mV VO MIN. +200 mV Pre-charge completed goal voltage -200 mV Pre-charge completed goal voltage +200 mV MIN. TYP. Note MAX. 40 70 50 60 Unit s s s s Note TYP. values are reference values when TA = 25C. 92 Data Sheet S15649EJ2V0DS PD161622 AC Characteristics (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 V to VCC1) (a) i80 series CPU interface RS tAS8 tf tr tAH8 /CS tCYC8 tCCLW, tCCLR /WR, /RD tCCHR, tCCHW tDS8 D0 to D15 (D7) (Write) tACC8 D0 to D15 (D7) (Read) tOH8 tDH8 Data Sheet S15649EJ2V0DS 93 PD161622 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 (normal write mode, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D15 D0 to D15 D0 to D15, CL = 100 pF D0 to D15, CL = 5 pF 10 Condition RS RS MIN. 0 0 250 60 140 60 80 60 0 110 100 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 VCC2 (normal write mode, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D15 D0 to D15 D0 to D15, CL = 100 pF D0 to D15, CL = 5 pF 10 Condition RS RS MIN. 0 0 333 60 160 100 140 60 0 150 150 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. 94 Data Sheet S15649EJ2V0DS PD161622 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 (high-speed RAM write mode, valid only for writing data R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control high-level pulse width (/WR) Data setup time Data hold time Symbol tAH8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 /WR /WR D0 to D15 D0 to D15 Condition RS RS MIN. 0 0 62 35 25 25 0 TYP. Note MAX. Unit ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 VCC2, (high-speed RAM write mode, valid only for writing data, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/WR) Control high-level pulse width (/WR) Data setup time Data hold time Symbol tAH8 tAS8 tCYC8 tCCLW tCCHW tDS8 tDH8 /WR /WR D0 to D15 D0 to D15 Condition RS RS MIN. 0 0 83 35 30 30 0 TYP. Note MAX. Unit ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Data Sheet S15649EJ2V0DS 95 PD161622 (b) M68 series CPU interface RS R,/W tAS6 tf tr tAH6 /CS tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 tDH6 D0 to D15 (D7) (Write) tACC6 D0 to D15 (D7) (Read) tOH6 96 Data Sheet S15649EJ2V0DS PD161622 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 (normal mode, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Read Write Enable low pulse width Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D15 D0 to D15 D0 to D15, CL = 100 pF D0 to D15, CL = 5 pF E E E E 10 140 120 80 60 Condition RS RS MIN. 0 0 250 80 0 110 100 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 VCC2 (normal mode, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Read Write Enable low pulse width Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D15 D0 to D15 D0 to D15, CL = 100 pF D0 to D15, CL = 5 pF E E E E 10 160 120 140 100 Condition RS RS MIN. 0 0 333 100 0 150 150 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. Data Sheet S15649EJ2V0DS 97 PD161622 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 (high-speed RAM write mode, valid only for writing data, R114 and R115 = 03H) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Enable high pulse width Enable low pulse width Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tEWHR tEWLR D0 to D15 D0 to D15 E E Condition RS RS MIN. 0 0 62 20 0 35 20 TYP. Note MAX. Unit ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 VCC2 (high-speed RAM write mode, valid only for writing data) Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Enable high pulse width Enable low pulse width Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tEWHR tEWLR D0 to D15 D0 to D15 E E Condition RS RS MIN. 0 0 83 30 0 40 30 TYP. Note MAX. Unit ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. 98 Data Sheet S15649EJ2V0DS PD161622 (c) Serial interface tCSS /CS tCSH tSAS RS tSCYC tSLW SCL tf tSDS SI tr tSAH tSHW tSDH VCC1 = 2.5 to 3.6 V, VCC2 = 1.7 to 2.5 V, VCC1 VCC2 Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI /CS /CS Condition MIN. 250 100 100 150 150 100 100 150 150 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI /CS /CS Condition MIN. 150 60 60 90 90 60 60 90 90 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Data Sheet S15649EJ2V0DS 99 PD161622 (d) Common Parameter Oscillation frequency Symbol fOSC1 fOSC2 Condition Internal oscillator (RSEL = L) External resistance connection oscillator (RSEL = H), R = 51 k Calibration setting time (frame frequency) Frame frequency tcal (fFRAME0) fFRAME1 fFRAME2 fFRAME3 Reset pulse width at power on Reset pulse width Reset time tVR tRW tR /RESET to interface operation Uncalibrated Calibrated Calibrated Note4 Note5 Note2 MIN. 250 TYP. Note1 MAX. 750 Unit kHz kHz 450 450 Note3 44 (128.4) 38 72 77 100 100 100 82.2 (68.7) 70 80 80 184 (32.6) 115 88 83 s (Hz) Hz Hz Hz ns ns ns VCC1 or VCC2 to /RESET Notes 1. TYP. values are reference values when TA = 25C. 2. The resistor value of "R" is depending on the characteristic of the parasitism capacity such as wiring. It is recommended to determine this value after through evaluation with actual system. 3. The relationship between the frame frequency and the calibration setting time is as follows. fFRAME0 = 1/tcal x 177 4. Measured at TA = -40 to +85C, after calibration at frame frequency = 80 Hz, TA = 25C exactly. 5. Measured at 5C, after calibration at frame frequency = 80 Hz exactly. 100 Data Sheet S15649EJ2V0DS PD161622 9. PD161622, 161640, and 161660 CONNECTION DIAGRAM EXAMPLE Connection diagram examples for the PD161622, 161640, and 161660 are show below. 1.7 V to VCC1 CPU RESET D0 to D15 /WR(R,/W) /RD(E) /CS An VDD 2.5 to 3.6 V RESET D0 to D15 /WR(R,/W) /RD(E) /CS VCC1 VCC1 RS VCC2 VS DCON VS 2.5 to 5.5 V VDC DCON RGONP VCE VCD11 VCD12 VCD2 LPM RGONP VCOMR VCOM VCOUT VCE VCD11 VCD12 VCD2 LPMP PD161660 VSS PD161622 VO VT GND(0 V) GCLK GSTB GOE1 GOE2 RGONG Y395 Y396 Y1 Y2 FBRSEL VSS LPMP COMMON O1 O2 TFT-LCD Panel 132 x RGB x 176 O176 Data Sheet S15649EJ2V0DS RGONG OE1 OE2 STVR(STVL) CLK VT VEE VCC1 LPM PD161640 SB VSS 101 PD161622 10. EXAMPLE of PD161622 and CPU CONNECTION Examples of PD161622 and CPU connection are shown below. In the example below, RS pin control in parallel interface mode is described for the case when the least significant bit of the address bus is being used. (1) i80 series format CPU PD161622 (2) M68 series format CPU PD161622 VDD2 VDD /CS A0 D0 to D15 /RD /WR /RESET VSS VDD1 /CS RS D0 to D15 /RD /WR /RESET VSS VDD /CS A0 D0 to D15 R,/W E /RESET VSS VDD2 VDD1 /CS RS D0 to D15 R,/W E /RESET VSS 102 Data Sheet S15649EJ2V0DS PD161622 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15649EJ2V0DS 103 |
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